Lines Matching refs:MESON_CLK_PLL_REG
96 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
97 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
98 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
100 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
101 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
110 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
111 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
112 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
113 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
114 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
115 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
129 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
130 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
131 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
132 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
135 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
136 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
137 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
141 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
142 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
143 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
Indexes created Sun Oct 19 02:09:48 GMT 2025