Lines Matching defs:CLK_DIV
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \
548 CLK_DIV("DIV_UARTA", "MUX_UARTA",
550 CLK_DIV("DIV_UARTB", "MUX_UARTB",
552 CLK_DIV("DIV_UARTC", "MUX_UARTC",
554 CLK_DIV("DIV_UARTD", "MUX_UARTD",
557 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1",
559 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2",
561 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3",
563 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4",
566 CLK_DIV("DIV_I2C1", "MUX_I2C1",
568 CLK_DIV("DIV_I2C2", "MUX_I2C2",
570 CLK_DIV("DIV_I2C3", "MUX_I2C3",
572 CLK_DIV("DIV_I2C4", "MUX_I2C4",
574 CLK_DIV("DIV_I2C5", "MUX_I2C5",
576 CLK_DIV("DIV_I2C6", "MUX_I2C6",
579 CLK_DIV("XUSB_HOST_SRC", "MUX_XUSB_HOST",
581 CLK_DIV("XUSB_SS_SRC", "MUX_XUSB_SS",
583 CLK_DIV("XUSB_FS_SRC", "MUX_XUSB_FS",
585 CLK_DIV("XUSB_FALCON_SRC", "MUX_XUSB_FALCON",
587 CLK_DIV("USB2_HSIC_TRK", "CLK_M",
589 CLK_DIV("DIV_PLL_U_OUT1", "PLL_U",
591 CLK_DIV("DIV_PLL_U_OUT2", "PLL_U",
594 CLK_DIV("DIV_MSELECT", "MUX_MSELECT",
597 CLK_DIV("DIV_TSENSOR", "MUX_TSENSOR",
599 CLK_DIV("DIV_SOC_THERM", "MUX_SOC_THERM",
602 CLK_DIV("DIV_HDA2CODEC_2X", "MUX_HDA2CODEC_2X",
604 CLK_DIV("DIV_HDA", "MUX_HDA",
607 CLK_DIV("DIV_SATA_OOB", "MUX_SATA_OOB",
609 CLK_DIV("DIV_SATA", "MUX_SATA",
Indexes created Tue Oct 07 21:09:53 GMT 2025