Cross Reference: /src/sys/arch/arm/nvidia/tegra210

Lines Matching defs:clk_parent
805 		struct clk *clk_parent = clk_get_parent(clk);
807 		    clk_parent ? clk_parent->name : "none");
825 	struct clk *clk, *clk_parent;
834 			clk_parent = clk_get(&sc->sc_clkdom,
836 			KASSERT(clk_parent != NULL);
838 			error = clk_set_parent(clk, clk_parent);
842 				    clk->name, clk_parent->name, error);
844 			clk_put(clk_parent);
1184 	struct clk *clk_parent;
1187 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1188 	if (clk_parent == NULL)
1190 	const u_int rate_parent = tegra210_car_clock_get_rate(sc, clk_parent);
1317 	struct clk *clk_parent;
1319 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1320 	if (clk_parent == NULL)
1322 	const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent);
1334 	struct clk *clk_parent;
1339 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1340 	const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent);
1389 	struct clk *clk_parent;
1395 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1396 	if (clk_parent == NULL)
1398 	const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent);
1494 	struct clk *clk_parent;
1503 		clk_parent = tegra210_car_clock_get_parent(priv, clk);
1504 		if (clk_parent == NULL)
1506 		return tegra210_car_clock_get_rate(priv, clk_parent);
1520 	struct clk *clk_parent;
1529 		clk_parent = tegra210_car_clock_get_parent(priv, clk);
1530 		if (clk_parent == NULL)
1532 		return tegra210_car_clock_set_rate(priv, clk_parent,
1549 	struct clk *clk_parent;
1552 		clk_parent = tegra210_car_clock_get_parent(priv, clk);
1553 		if (clk_parent == NULL)
1555 		return tegra210_car_clock_enable(priv, clk_parent);
1574     struct clk *clk_parent)
1577 	struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent);
1582 		if (nclk_parent == clk_parent || nclk_parent == NULL)
1585 		    clk_parent);
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