Home | History | Annotate | Download | only in nvidia

Lines Matching defs:tpll

1143 	struct tegra_pll_clk *tpll = &tclk->u.pll;
1158 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1159 divm = __SHIFTOUT(base, tpll->divm_mask);
1160 divn = __SHIFTOUT(base, tpll->divn_mask);
1161 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1162 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1163 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) {
1166 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) {
1168 divm *= __SHIFTOUT(base, tpll->divp_mask);
1170 divp = __SHIFTOUT(base, tpll->divp_mask);
1181 struct tegra_pll_clk *tpll = &tclk->u.pll;
1194 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1221 base = bus_space_read_4(bst, bsh, tpll->base_reg);
1234 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1240 tegra_reg_set_clear(bst, bsh, tpll->base_reg,