Lines Matching refs:_name
304 #define CLK_FIXED(_name, _rate) { \
305 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \
309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
310 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \
322 #define CLK_MUX(_name, _reg, _bits, _p) { \
323 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \
334 #define CLK_FIXED_DIV(_name, _parent, _div) { \
335 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \
345 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \
355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
368 #define CLK_GATE_L(_name, _parent, _bits) \
369 CLK_GATE(_name, _parent, \
373 #define CLK_GATE_H(_name, _parent, _bits) \
374 CLK_GATE(_name, _parent, \
378 #define CLK_GATE_U(_name, _parent, _bits) \
379 CLK_GATE(_name, _parent, \
383 #define CLK_GATE_V(_name, _parent, _bits) \
384 CLK_GATE(_name, _parent, \
388 #define CLK_GATE_W(_name, _parent, _bits) \
389 CLK_GATE(_name, _parent, \
393 #define CLK_GATE_X(_name, _parent, _bits) \
394 CLK_GATE(_name, _parent, \
398 #define CLK_GATE_Y(_name, _parent, _bits) \
399 CLK_GATE(_name, _parent, \
404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \
405 CLK_GATE(_name, _parent, _reg, _reg, _bits)
Indexes created Wed Oct 15 16:09:53 GMT 2025