Lines Matching refs:_parent
309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
311 .parent = (_parent), \
334 #define CLK_FIXED_DIV(_name, _parent, _div) { \
336 .parent = (_parent), \
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \
346 .parent = (_parent), \
355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
358 .parent = (_parent), \
368 #define CLK_GATE_L(_name, _parent, _bits) \
369 CLK_GATE(_name, _parent, \
373 #define CLK_GATE_H(_name, _parent, _bits) \
374 CLK_GATE(_name, _parent, \
378 #define CLK_GATE_U(_name, _parent, _bits) \
379 CLK_GATE(_name, _parent, \
383 #define CLK_GATE_V(_name, _parent, _bits) \
384 CLK_GATE(_name, _parent, \
388 #define CLK_GATE_W(_name, _parent, _bits) \
389 CLK_GATE(_name, _parent, \
393 #define CLK_GATE_X(_name, _parent, _bits) \
394 CLK_GATE(_name, _parent, \
398 #define CLK_GATE_Y(_name, _parent, _bits) \
399 CLK_GATE(_name, _parent, \
404 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \
405 CLK_GATE(_name, _parent, _reg, _reg, _bits)
Indexes created Mon Oct 27 20:09:55 GMT 2025