Cross Reference: /src/sys/arch/arm/nvidia/tegra210

Lines Matching refs:tclk
1100 	struct tegra_clk *tclk;
1108 	tclk = tegra210_car_clock_find_by_id(clock_id);
1109 	if (tclk)
1110 		return TEGRA_CLK_BASE(tclk);
1118 	struct tegra_clk *tclk;
1120 	tclk = tegra210_car_clock_find(name);
1121 	if (tclk == NULL)
1124 	atomic_inc_uint(&tclk->refcnt);
1126 	return TEGRA_CLK_BASE(tclk);
1132 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1134 	KASSERT(tclk->refcnt > 0);
1136 	atomic_dec_uint(&tclk->refcnt);
1141     struct tegra_clk *tclk)
1143 	struct tegra_pll_clk *tpll = &tclk->u.pll;
1150 	KASSERT(tclk->type == TEGRA_CLK_PLL);
1152 	tclk_parent = tegra210_car_clock_find(tclk->parent);
1179     struct tegra_clk *tclk, u_int rate)
1181 	struct tegra_pll_clk *tpll = &tclk->u.pll;
1187 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1252 		    tclk->base.name, rate);
1260     struct tegra_clk *tclk, struct tegra_clk *tclk_parent)
1262 	struct tegra_mux_clk *tmux = &tclk->u.mux;
1268 	KASSERT(tclk->type == TEGRA_CLK_MUX);
1292     struct tegra_clk *tclk)
1294 	struct tegra_mux_clk *tmux = &tclk->u.mux;
1298 	KASSERT(tclk->type == TEGRA_CLK_MUX);
1314     struct tegra_clk *tclk)
1316 	struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div;
1319 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1329     struct tegra_clk *tclk)
1331 	struct tegra_div_clk *tdiv = &tclk->u.div;
1337 	KASSERT(tclk->type == TEGRA_CLK_DIV);
1339 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1384     struct tegra_clk *tclk, u_int rate)
1386 	struct tegra_div_clk *tdiv = &tclk->u.div;
1393 	KASSERT(tclk->type == TEGRA_CLK_DIV);
1395 	clk_parent = tegra210_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1461     struct tegra_clk *tclk, bool enable)
1463 	struct tegra_gate_clk *tgate = &tclk->u.gate;
1468 	KASSERT(tclk->type == TEGRA_CLK_GATE);
1493 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1496 	switch (tclk->type) {
1498 		return tclk->u.fixed.rate;
1500 		return tegra210_car_clock_get_rate_pll(priv, tclk);
1508 		return tegra210_car_clock_get_rate_fixed_div(priv, tclk);
1510 		return tegra210_car_clock_get_rate_div(priv, tclk);
1512 		panic("tegra210: unknown tclk type %d", tclk->type);
1519 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1524 	switch (tclk->type) {
1533 		    rate * tclk->u.fixed_div.div);
1537 		return tegra210_car_clock_set_rate_pll(priv, tclk, rate);
1539 		return tegra210_car_clock_set_rate_div(priv, tclk, rate);
1541 		panic("tegra210: unknown tclk type %d", tclk->type);
1548 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1551 	if (tclk->type != TEGRA_CLK_GATE) {
1558 	return tegra210_car_clock_enable_gate(priv, tclk, true);
1564 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1566 	if (tclk->type != TEGRA_CLK_GATE)
1569 	return tegra210_car_clock_enable_gate(priv, tclk, false);
1576 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1580 	if (tclk->type != TEGRA_CLK_MUX) {
1588 	return tegra210_car_clock_set_parent_mux(priv, tclk, tclk_parent);
1594 	struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1597 	switch (tclk->type) {
1603 		if (tclk->parent) {
1604 			tclk_parent = tegra210_car_clock_find(tclk->parent);
1608 		tclk_parent = tegra210_car_clock_get_parent_mux(priv, tclk);
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