Lines Matching refs:tegra_reg_set_clear
876 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG,
878 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG3_REG,
880 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG,
884 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
886 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
888 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
890 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
892 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
907 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
918 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG, 0,
920 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG,
922 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG,
924 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG,
926 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG,
928 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG,
931 tegra_reg_set_clear(bst, bsh, CAR_UTMIPLL_HW_PWRDN_CFG0_REG,
945 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_OVERRIDE, 0);
946 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, CAR_PLLU_MISC_IDDQ, 0);
947 tegra_reg_set_clear(bst, bsh, CAR_PLLU_MISC_REG, 0, CAR_PLLU_MISC_IDDQ);
948 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT1_RSTN);
949 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, 0, CAR_PLLU_OUTA_OUT2_RSTN);
951 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG,
956 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_ENABLE, 0);
961 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_ICUSB, 0);
962 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_HSIC, 0);
963 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, CAR_PLLU_BASE_CLKENABLE_USB, 0);
964 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_RSTN, 0);
965 tegra_reg_set_clear(bst, bsh, CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT2_RSTN, 0);
971 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_OVERRIDE);
972 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG,
978 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG, 0,
981 tegra_reg_set_clear(bst, bsh, CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG,
984 tegra_reg_set_clear(bst, bsh, CAR_PLLU_BASE_REG, 0, CAR_PLLU_BASE_CLKENABLE_USB);
989 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
992 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG,
1001 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG,
1011 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SEL_PLLREFE);
1012 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_REF_SRC);
1013 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_OVERRIDE);
1015 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG,
1022 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG,
1025 tegra_reg_set_clear
1030 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG,
1042 tegra_reg_set_clear(bst, bsh, CAR_PLLE_SS_CNTL_REG, 0, CAR_PLLE_SS_CNTL_INTERP_RESET);
1043 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG, 0, CAR_PLLE_MISC_IDDQ_SWCTL);
1044 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_SS_SWCTL);
1045 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, 0, CAR_PLLE_AUX_ENABLE_SWCTL);
1046 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SS_SEQ_INCLUDE, 0);
1047 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_USE_LOCKDET, 0);
1049 tegra_reg_set_clear(bst, bsh, CAR_PLLE_AUX_REG, CAR_PLLE_AUX_SEQ_ENABLE, 0);
1062 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
1217 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG,
1240 tegra_reg_set_clear(bst, bsh, tpll->base_reg,
1681 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
1685 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
1700 tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
1713 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
1716 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
1731 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
Indexes created Sun Oct 19 01:09:53 GMT 2025