Lines Matching refs:__BITS
34 #define TEGRA_SATA_FPCI_BAR_START __BITS(31,4)
55 #define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13)
67 #define TEGRA_T_SATA0_NVOOB_COMMA_CNT __BITS(30,28)
68 #define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH __BITS(27,26)
69 #define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE __BITS(25,24)
80 #define TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW __BITS(26,18)
89 #define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE __BITS(31,16)
90 #define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF __BITS(15,8)
105 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_DRV_CNTL __BITS(27,24)
106 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_PRE __BITS(23,20)
107 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_CMADJ __BITS(19,16)
108 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK __BITS(15,8)
109 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP __BITS(7,0)
112 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_DRV_CNTL __BITS(27,24)
113 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_PRE __BITS(23,20)
114 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK __BITS(19,12)
115 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_CMADJ __BITS(11,8)
116 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP __BITS(7,0)
119 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN3 __BITS(23,16)
120 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN2 __BITS(15,8)
121 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 __BITS(7,0)
124 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ __BITS(31,16)
125 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN1_RX_EQ __BITS(15,0)
Indexes created Fri Oct 17 23:09:53 GMT 2025