1 /* $NetBSD: tegra_ahcisatareg.h,v 1.3 2018/12/14 12:29:22 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_TEGRA_AHCISATAREG_H 30 #define _ARM_TEGRA_AHCISATAREG_H 31 32 #define TEGRA_SATA_FPCI_BAR5_REG 0x94 33 34 #define TEGRA_SATA_FPCI_BAR_START __BITS(31,4) 35 #define TEGRA_SATA_FPCI_BAR_ACCESS_TYPE __BIT(0) 36 37 #define TEGRA_SATA_CONFIGURATION_REG 0x180 38 #define TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE __BIT(31) 39 #define TEGRA_SATA_CONFIGURATION_EN_FPCI __BIT(0) 40 41 #define TEGRA_SATA_INTR_MASK_REG 0x188 42 #define TEGRA_SATA_INTR_MASK_IP_INT __BIT(16) 43 #define TEGRA_SATA_INTR_MASK_MSI __BIT(8) 44 #define TEGRA_SATA_INTR_MASK_INT __BIT(0) 45 46 #define TEGRA_T_SATA0_CFG1_REG 0x1004 47 #define TEGRA_T_SATA0_CFG1_INTR_DISABLE __BIT(10) 48 #define TEGRA_T_SATA0_CFG1_SERR __BIT(8) 49 #define TEGRA_T_SATA0_CFG1_BUS_MASTER __BIT(2) 50 #define TEGRA_T_SATA0_CFG1_MEM_SPACE __BIT(1) 51 #define TEGRA_T_SATA0_CFG1_IO_SPACE __BIT(0) 52 53 54 #define TEGRA_T_SATA0_CFG9_REG 0x1024 55 #define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13) 56 #define TEGRA_T_SATA0_CFG9_SPACE_TYPE __BIT(0) 57 58 #define TEGRA_SATA_AUX_MISC_CNTL_1_REG 0x1108 59 #define TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL __BIT(18) 60 #define TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT __BIT(13) 61 #define TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR __BIT(7) 62 63 #define TEGRA_SATA_AUX_RX_STAT_INT_REG 0x110c 64 #define TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE __BIT(2) 65 66 #define TEGRA_T_SATA0_NVOOB_REG 0x1114 67 #define TEGRA_T_SATA0_NVOOB_COMMA_CNT __BITS(30,28) 68 #define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH __BITS(27,26) 69 #define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE __BITS(25,24) 70 71 #define TEGRA_T_SATA0_CFG_PHY_0_REG 0x1120 72 #define TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH __BIT(24) 73 #define TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD __BIT(11) 74 75 #define TEGRA_T_SATA0_CFG_PHY_1_REG 0x112c 76 #define TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN __BIT(23) 77 #define TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN __BIT(22) 78 79 #define TEGRA_T_SATA0_CFG_2NVOOB_2_REG 0x1134 80 #define TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW __BITS(26,18) 81 82 #define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_REG 0x1300 83 #define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP __BIT(26) 84 #define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM __BIT(17) 85 #define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP __BIT(14) 86 #define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP __BIT(13) 87 88 #define TEGRA_T_SATA0_BKDOOR_CC_REG 0x14a4 89 #define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE __BITS(31,16) 90 #define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF __BITS(15,8) 91 92 #define TEGRA_T_SATA0_CFG_POWER_GATE_REG 0x14ac 93 #define TEGRA_T_SATA0_CFG_POWER_GATE_SSTS_RESTORED __BIT(23) 94 95 #define TEGRA_T_SATA0_CFG_SATA_REG 0x154c 96 #define TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN __BIT(12) 97 98 #define TEGRA_T_SATA0_INDEX_REG 0x1680 99 #define TEGRA_T_SATA0_INDEX_CH4 __BIT(3) 100 #define TEGRA_T_SATA0_INDEX_CH3 __BIT(2) 101 #define TEGRA_T_SATA0_INDEX_CH2 __BIT(1) 102 #define TEGRA_T_SATA0_INDEX_CH1 __BIT(0) 103 104 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG 0x1690 105 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_DRV_CNTL __BITS(27,24) 106 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_PRE __BITS(23,20) 107 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_CMADJ __BITS(19,16) 108 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK __BITS(15,8) 109 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP __BITS(7,0) 110 111 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG 0x1694 112 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_DRV_CNTL __BITS(27,24) 113 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_PRE __BITS(23,20) 114 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK __BITS(19,12) 115 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_CMADJ __BITS(11,8) 116 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP __BITS(7,0) 117 118 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_REG 0x169c 119 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN3 __BITS(23,16) 120 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN2 __BITS(15,8) 121 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 __BITS(7,0) 122 123 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_REG 0x16d0 124 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ __BITS(31,16) 125 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN1_RX_EQ __BITS(15,0) 126 127 #define TEGRA_T_SATA0_CHX_PHY_CTRL17_REG 0x16e8 128 #define TEGRA_T_SATA0_CHX_PHY_CTRL18_REG 0x16ec 129 #define TEGRA_T_SATA0_CHX_PHY_CTRL19_REG 0x16f0 130 #define TEGRA_T_SATA0_CHX_PHY_CTRL20_REG 0x16f4 131 #define TEGRA_T_SATA0_CHX_PHY_CTRL21_REG 0x16f8 132 133 #endif /* _ARM_TEGRA_AHCISATAREG_H */ 134
Indexes created Thu Sep 25 08:09:54 GMT 2025