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Lines Matching refs:sc

60 	struct sdhc_softc	sc;
98 	struct tegra_sdhc_softc * const sc = device_private(self);
114 	sc->sc.sc_dev = self;
115 	sc->sc.sc_dmat = faa->faa_dmat;
119 	    &sc->sc.sc_dmat, BUS_DMA_WAITOK);
126 	sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS |
135 		sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
137 	sc->sc.sc_host = &sc->sc_host;
139 	sc->sc_bst = faa->faa_bst;
140 	error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
145 	sc->sc_bsz = size;
149 	sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS;
150 	sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
152 	sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
154 	sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP;
157 	sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle,
159 	if (sc->sc_pin_power)
160 		fdtbus_gpio_write(sc->sc_pin_power, 1);
162 	sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle,
164 	sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle,
167 	if (sc->sc_pin_cd) {
168 		sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect;
169 		sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET;
171 	if (sc->sc_pin_wp) {
172 		sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect;
175 	sc->sc_reg_vqmmc = fdtbus_regulator_acquire(faa->faa_phandle,
177 	if (sc->sc_reg_vqmmc) {
178 		sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage;
181 		sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS;
182 		sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
184 		sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
186 		sc->sc.sc_caps2 &= ~(SDHC_SDR50_SUPP|SDHC_SDR104_SUPP|SDHC_DDR50_SUPP);
189 	sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0);
190 	if (sc->sc_clk == NULL) {
194 	sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci");
195 	if (sc->sc_rst == NULL) {
200 	fdtbus_reset_assert(sc->sc_rst);
202 	error = clk_set_rate(sc->sc_clk, 100000000);
204 	error = clk_set_rate(sc->sc_clk, 204000000);
210 	error = clk_enable(sc->sc_clk);
215 	fdtbus_reset_deassert(sc->sc_rst);
217 	sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000;
220 	aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase);
222 	if (sc->sc.sc_clkbase == 0) {
232 	sc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_SDMMC,
233 	    0, sdhc_intr, &sc->sc, device_xname(self));
234 	if (sc->sc_ih == NULL) {
241 	error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz);
245 		fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih);
246 		sc->sc_ih = NULL;
254 	struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
256 	KASSERT(sc->sc_pin_cd != NULL);
258 	return fdtbus_gpio_read(sc->sc_pin_cd);
264 	struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
266 	KASSERT(sc->sc_pin_wp != NULL);
268 	return fdtbus_gpio_read(sc->sc_pin_wp);
274 	struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev);
278 	KASSERT(sc->sc_reg_vqmmc != NULL);
291 	error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol);
295 	return fdtbus_regulator_enable(sc->sc_reg_vqmmc);