Lines Matching refs:fpcih
517 const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
525 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG);
527 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv);
532 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG);
535 fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG);
538 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val);
593 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG,
630 const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
655 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
656 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG,
659 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG));
662 bus_space_read_4(bst, fpcih, PCI_BAR0));
664 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000);
666 bus_space_read_4(bst, fpcih, PCI_BAR0));
675 bus_space_read_4(bst, fpcih, 0x1bc));
676 bus_space_write_4(bst, fpcih, 0x1bc, 0x80);
678 bus_space_read_4(bst, fpcih, 0x1bc));
926 const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
928 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range);
929 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset);
939 const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
941 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range);
942 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value);
950 const bus_space_handle_t fpcih = psc->sc_bsh_fpci;
957 val = bus_space_read_4(bst, fpcih,
965 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG,
968 val = bus_space_read_4(bst, fpcih,
979 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg);
981 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG,
988 val = bus_space_read_4(bst, fpcih,
998 val = bus_space_read_4(bst, fpcih,
Indexes created Tue Oct 28 12:10:06 GMT 2025