Lines Matching refs:__BIT
36 #define SRC_SCR_DBG_RST_MASK_PG __BIT(25)
38 #define SRC_SCR_COREN_ENABLE(n) __BIT(22 + ((n) - 1)) /* no core0 bit */
39 #define SRC_SCR_CORE3_ENABLE __BIT(24)
40 #define SRC_SCR_CORE2_ENABLE __BIT(23)
41 #define SRC_SCR_CORE1_ENABLE __BIT(22)
42 #define SRC_SCR_CORES_DBG_RST __BIT(21)
43 #define SRC_SCR_COREN_DBG_RST(n) __BIT(17 + (n))
44 #define SRC_SCR_CORE3_DBG_RST __BIT(20)
45 #define SRC_SCR_CORE2_DBG_RST __BIT(19)
46 #define SRC_SCR_CORE1_DBG_RST __BIT(18)
47 #define SRC_SCR_CORE0_DBG_RST __BIT(17)
48 #define SRC_SCR_COREN_RST(n) __BIT(13 + (n))
49 #define SRC_SCR_CORE3_RST __BIT(16)
50 #define SRC_SCR_CORE2_RST __BIT(15)
51 #define SRC_SCR_CORE1_RST __BIT(14)
52 #define SRC_SCR_CORE0_RST __BIT(13)
53 #define SRC_SCR_SW_IPU2_RST __BIT(12)
54 #define SRC_SCR_EIM_RST __BIT(11)
57 #define SRC_SCR_SW_OPEN_VG_RS __BIT(4)
58 #define SRC_SCR_SW_IPU1_RST __BIT(3)
59 #define SRC_SCR_SW_VPU_RST __BIT(2)
60 #define SRC_SCR_SW_GPU_RST __BIT(1)
61 #define SRC_SCR_WARM_RESET_ENABLE __BIT(0)
64 #define SRC_SRSR_WARM_BOOT __BIT(16)
66 #define SRC_SRSR_JTAG_SW_RST __BIT(6)
67 #define SRC_SRSR_JTAG_RST_B __BIT(5)
68 #define SRC_SRSR_WDOG_RST_B __BIT(4)
69 #define SRC_SRSR_IPP_USER_RESET_ __BIT(3)
70 #define SRC_SRSR_CSU_RESET_B __BIT(2)
71 #define SRC_SRSR_RESERVED1 __BIT(1)
72 #define SRC_SRSR_IPP_RESET_B __BIT(0)
74 #define SRC_SISR_CORE3_WDOG_RST_REQ __BIT(8)
75 #define SRC_SISR_CORE2_WDOG_RST_REQ __BIT(7)
76 #define SRC_SISR_CORE1_WDOG_RST_REQ __BIT(6)
77 #define SRC_SISR_CORE0_WDOG_RST_REQ __BIT(5)
78 #define SRC_SISR_IPU2_PASSED_RESET __BIT(4)
79 #define SRC_SISR_OPEN_VG_PASSED_RESET __BIT(3)
80 #define SRC_SISR_IPU1_PASSED_RESET __BIT(2)
81 #define SRC_SISR_VPU_PASSED_RESET __BIT(1)
82 #define SRC_SISR_GPU_PASSED_RESET __BIT(0)
101 #define SRC_GPR10_CORE3_ERROR_STATUS __BIT(27)
102 #define SRC_GPR10_CORE2_ERROR_STATUS __BIT(26)
103 #define SRC_GPR10_CORE1_ERROR_STATUS __BIT(25)
Indexes created Sun Oct 19 02:09:48 GMT 2025