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      1 /*	$NetBSD: imx6_srcreg.h,v 1.2 2024/02/07 04:20:27 msaitoh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2014 Ryo Shimizu
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     25  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _IMX6_SRCREG_H_
     30 #define _IMX6_SRCREG_H_
     31 
     32 #include <sys/cdefs.h>
     33 
     34 /* SRC - System Reset Controller */
     35 #define SRC_SCR					0x00000000
     36 #define  SRC_SCR_DBG_RST_MASK_PG		__BIT(25)
     37 
     38 #define  SRC_SCR_COREN_ENABLE(n)		__BIT(22 + ((n) - 1))	/* no core0 bit */
     39 #define  SRC_SCR_CORE3_ENABLE			__BIT(24)
     40 #define  SRC_SCR_CORE2_ENABLE			__BIT(23)
     41 #define  SRC_SCR_CORE1_ENABLE			__BIT(22)
     42 #define  SRC_SCR_CORES_DBG_RST			__BIT(21)
     43 #define  SRC_SCR_COREN_DBG_RST(n)		__BIT(17 + (n))
     44 #define  SRC_SCR_CORE3_DBG_RST			__BIT(20)
     45 #define  SRC_SCR_CORE2_DBG_RST			__BIT(19)
     46 #define  SRC_SCR_CORE1_DBG_RST			__BIT(18)
     47 #define  SRC_SCR_CORE0_DBG_RST			__BIT(17)
     48 #define  SRC_SCR_COREN_RST(n)			__BIT(13 + (n))
     49 #define  SRC_SCR_CORE3_RST			__BIT(16)
     50 #define  SRC_SCR_CORE2_RST			__BIT(15)
     51 #define  SRC_SCR_CORE1_RST			__BIT(14)
     52 #define  SRC_SCR_CORE0_RST			__BIT(13)
     53 #define  SRC_SCR_SW_IPU2_RST			__BIT(12)
     54 #define  SRC_SCR_EIM_RST			__BIT(11)
     55 #define  SRC_SCR_MASK_WDOG_RST			__BITS(10, 7)
     56 #define  SRC_SCR_WARM_RST_BYPASS_COUNT		__BITS(6, 5)
     57 #define  SRC_SCR_SW_OPEN_VG_RS			__BIT(4)
     58 #define  SRC_SCR_SW_IPU1_RST			__BIT(3)
     59 #define  SRC_SCR_SW_VPU_RST			__BIT(2)
     60 #define  SRC_SCR_SW_GPU_RST			__BIT(1)
     61 #define  SRC_SCR_WARM_RESET_ENABLE		__BIT(0)
     62 #define SRC_SBMR1				0x00000004
     63 #define SRC_SRSR				0x00000008
     64 #define  SRC_SRSR_WARM_BOOT			__BIT(16)
     65 #define  SRC_SRSR_RESERVED7			__BITS(15, 7)
     66 #define  SRC_SRSR_JTAG_SW_RST			__BIT(6)
     67 #define  SRC_SRSR_JTAG_RST_B			__BIT(5)
     68 #define  SRC_SRSR_WDOG_RST_B			__BIT(4)
     69 #define  SRC_SRSR_IPP_USER_RESET_		__BIT(3)
     70 #define  SRC_SRSR_CSU_RESET_B			__BIT(2)
     71 #define  SRC_SRSR_RESERVED1			__BIT(1)
     72 #define  SRC_SRSR_IPP_RESET_B			__BIT(0)
     73 #define SRC_SISR				0x00000014
     74 #define  SRC_SISR_CORE3_WDOG_RST_REQ		__BIT(8)
     75 #define  SRC_SISR_CORE2_WDOG_RST_REQ		__BIT(7)
     76 #define  SRC_SISR_CORE1_WDOG_RST_REQ		__BIT(6)
     77 #define  SRC_SISR_CORE0_WDOG_RST_REQ		__BIT(5)
     78 #define  SRC_SISR_IPU2_PASSED_RESET		__BIT(4)
     79 #define  SRC_SISR_OPEN_VG_PASSED_RESET		__BIT(3)
     80 #define  SRC_SISR_IPU1_PASSED_RESET		__BIT(2)
     81 #define  SRC_SISR_VPU_PASSED_RESET		__BIT(1)
     82 #define  SRC_SISR_GPU_PASSED_RESET		__BIT(0)
     83 #define SRC_SIMR				0x00000018
     84 #define  SRC_SIMR_MASK_IPU2_PASSED_RESET	_BIT(4)
     85 #define  SRC_SIMR_MASK_OPEN_VG_PASSED_RESET	_BIT(3)
     86 #define  SRC_SIMR_MASK_IPU_PASSED_RESET		_BIT(2)
     87 #define  SRC_SIMR_MASK_VPU_PASSED_RESET		_BIT(1)
     88 #define  SRC_SIMR_MASK_GPU_PASSED_RESET		_BIT(0)
     89 #define SRC_SBMR2				0x0000001c
     90 #define SRC_GPRN_ENTRY(n)			(0x20 + (8 * (n)))
     91 #define SRC_GPR1				0x00000020 /* core0 entry */
     92 #define SRC_GPR2				0x00000024
     93 #define SRC_GPR3				0x00000028 /* core1 entry */
     94 #define SRC_GPR4				0x0000002c
     95 #define SRC_GPR5				0x00000030 /* core2 entry */
     96 #define SRC_GPR6				0x00000034
     97 #define SRC_GPR7				0x00000038 /* core3 entry */
     98 #define SRC_GPR8				0x0000003c
     99 #define SRC_GPR9				0x00000040
    100 #define SRC_GPR10				0x00000044
    101 #define  SRC_GPR10_CORE3_ERROR_STATUS		__BIT(27)
    102 #define  SRC_GPR10_CORE2_ERROR_STATUS		__BIT(26)
    103 #define  SRC_GPR10_CORE1_ERROR_STATUS		__BIT(25)
    104 
    105 #endif /* _IMX6_SRCREG_H_ */
    106