Lines Matching defs:CLKGATE_CON
46 #define CLKGATE_CON(n) (0x0200 + (n) * 4)
204 CLKGATE_CON(8), /* gate_reg */
211 CLKGATE_CON(8), /* gate_reg */
218 CLKGATE_CON(8), /* gate_reg */
225 CLKGATE_CON(2), /* gate_reg */
232 CLKGATE_CON(2), /* gate_reg */
245 CLKGATE_CON(10), /* gate_reg */
252 CLKGATE_CON(10), /* gate_reg */
259 CLKGATE_CON(4), /* gate_reg */
266 CLKGATE_CON(4), /* gate_reg */
273 CLKGATE_CON(4), /* gate_reg */
280 CLKGATE_CON(1), /* gate_reg */
287 CLKGATE_CON(2), /* gate_reg */
294 CLKGATE_CON(2), /* gate_reg */
301 CLKGATE_CON(3), /* gate_reg */
308 CLKGATE_CON(9), /* gate_reg */
315 CLKGATE_CON(3), /* gate_reg */
322 CLKGATE_CON(3), /* gate_reg */
329 CLKGATE_CON(2), /* gate_reg */
336 CLKGATE_CON(2), /* gate_reg */
343 CLKGATE_CON(2), /* gate_reg */
350 CLKGATE_CON(2), /* gate_reg */
357 CLKGATE_CON(2), /* gate_reg */
364 CLKGATE_CON(2), /* gate_reg */
370 RK_GATE(0, "apll_core", "apll", CLKGATE_CON(0), 0),
371 RK_GATE(0, "dpll_core", "dpll", CLKGATE_CON(0), 1),
372 RK_GATE(0, "gpll_core", "gpll", CLKGATE_CON(0), 2),
373 RK_GATE(0, "npll_core", "npll", CLKGATE_CON(0), 12),
374 RK_GATE(0, "gpll_peri", "gpll", CLKGATE_CON(4), 0),
375 RK_GATE(0, "cpll_peri", "cpll", CLKGATE_CON(4), 1),
376 RK_GATE(0, "hdmiphy_peri", "hdmiphy", CLKGATE_CON(4), 2),
377 RK_GATE(0, "pclk_bus", "pclk_bus_pre", CLKGATE_CON(8), 3),
378 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLKGATE_CON(8), 4),
379 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLKGATE_CON(10), 0),
380 RK_GATE(RK3328_PCLK_I2C0, "pclk_i2c0", "pclk_bus", CLKGATE_CON(15), 10),
381 RK_GATE(RK3328_PCLK_I2C1, "pclk_i2c1", "pclk_bus", CLKGATE_CON(16), 0),
382 RK_GATE(RK3328_PCLK_I2C2, "pclk_i2c2", "pclk_bus", CLKGATE_CON(16), 1),
383 RK_GATE(RK3328_PCLK_I2C3, "pclk_i2c3", "pclk_bus", CLKGATE_CON(16), 2),
384 RK_GATE(RK3328_PCLK_SPI, "pclk_spi", "pclk_bus", CLKGATE_CON(16), 5),
385 RK_GATE(RK3328_PCLK_PWM, "pclk_rk_pwm", "pclk_bus", CLKGATE_CON(16), 6),
386 RK_GATE(RK3328_PCLK_GPIO0, "pclk_gpio0", "pclk_bus", CLKGATE_CON(16), 7),
387 RK_GATE(RK3328_PCLK_GPIO1, "pclk_gpio1", "pclk_bus", CLKGATE_CON(16), 8),
388 RK_GATE(RK3328_PCLK_GPIO2, "pclk_gpio2", "pclk_bus", CLKGATE_CON(16), 9),
389 RK_GATE(RK3328_PCLK_GPIO3, "pclk_gpio3", "pclk_bus", CLKGATE_CON(16), 10),
390 CLKGATE_CON(16), 11),
391 RK_GATE(RK3328_PCLK_UART1, "pclk_uart1", "pclk_bus", CLKGATE_CON(16), 12),
392 RK_GATE(RK3328_PCLK_UART2, "pclk_uart2", "pclk_bus", CLKGATE_CON(16), 13),
393 RK_GATE(RK3328_PCLK_TSADC, "pclk_tsadc", "pclk_bus", CLKGATE_CON(16), 14),
394 RK_GATE(RK3328_SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", CLKGATE_CON(9), 7),
395 RK_GATE(RK3328_SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", CLKGATE_CON(9), 4),
396 RK_GATE(RK3328_SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", CLKGATE_CON(9), 5),
397 RK_GATE(RK3328_SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", CLKGATE_CON(9), 6),
398 RK_GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLKGATE_CON(15), 15),
399 RK_GATE(RK3328_ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", CLKGATE_CON(19), 4),
400 RK_GATE(RK3328_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", CLKGATE_CON(19), 0),
401 RK_GATE(RK3328_HCLK_SDIO, "hclk_sdio", "hclk_peri", CLKGATE_CON(19), 1),
402 RK_GATE(RK3328_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(19), 2),
403 RK_GATE(RK3328_HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", CLKGATE_CON(19), 15),
404 RK_GATE(RK3328_HCLK_HOST0, "hclk_host0", "hclk_peri", CLKGATE_CON(19), 6),
405 RK_GATE(RK3328_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLKGATE_CON(19), 7),
406 RK_GATE(RK3328_HCLK_OTG, "hclk_otg", "hclk_peri", CLKGATE_CON(19), 8),
407 RK_GATE(RK3328_HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", CLKGATE_CON(19), 9),
408 RK_GATE(RK3328_ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", CLKGATE_CON(26), 2),
409 RK_GATE(RK3328_PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", CLKGATE_CON(26), 3),
410 RK_GATE(0, "aclk_gmac_niu", "aclk_gmac", CLKGATE_CON(26), 4),
411 RK_GATE(0, "pclk_gmac_niu", "pclk_gmac", CLKGATE_CON(26), 5),
426 CLKGATE_CON(1), /* gate_reg */
433 CLKGATE_CON(1), /* gate_reg */
440 CLKGATE_CON(1), /* gate_reg */
447 CLKGATE_CON(1), /* gate_reg */
466 RK_GATE(RK3328_SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(1), 3),
467 RK_GATE(RK3328_SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(1), 6),
468 RK_GATE(RK3328_SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(1), 10),
469 RK_GATE(RK3328_SCLK_SPDIF, "clk_spdif", "clk_spdif_mux", CLKGATE_CON(1), 12),
470 RK_GATE(RK3328_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_bus_pre", CLKGATE_CON(15), 3),
471 RK_GATE(RK3328_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_bus_pre", CLKGATE_CON(15), 4),
472 RK_GATE(RK3328_HCLK_I2S2_2CH, "hclk_i2s2", "hclk_bus_pre", CLKGATE_CON(15), 5),
473 RK_GATE(RK3328_HCLK_SPDIF_8CH, "hclk_spdif", "hclk_bus_pre", CLKGATE_CON(15), 6),
474 RK_GATE(RK3328_HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", CLKGATE_CON(15), 7),
475 RK_GATE(RK3328_HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", CLKGATE_CON(15), 8),
480 CLKGATE_CON(7), /* gate_reg */
487 CLKGATE_CON(11), /* gate_reg */
Indexes created Tue Oct 07 21:09:53 GMT 2025