1 /* $NetBSD: rk3328_cru.c,v 1.10 2023/04/24 05:16:01 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.10 2023/04/24 05:16:01 mrg Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3328_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define MISC_CON 0x0084 45 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 46 #define CLKGATE_CON(n) (0x0200 + (n) * 4) 47 #define SOFTRST_CON(n) (0x0300 + (n) * 4) 48 49 #define GRF_SOC_CON4 0x0410 50 #define GRF_MAC_CON1 0x0904 51 52 static int rk3328_cru_match(device_t, cfdata_t, void *); 53 static void rk3328_cru_attach(device_t, device_t, void *); 54 55 static const struct device_compatible_entry compat_data[] = { 56 { .compat = "rockchip,rk3328-cru" }, 57 DEVICE_COMPAT_EOL 58 }; 59 60 CFATTACH_DECL_NEW(rk3328_cru, sizeof(struct rk_cru_softc), 61 rk3328_cru_match, rk3328_cru_attach, NULL, NULL); 62 63 static const struct rk_cru_pll_rate pll_rates[] = { 64 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 65 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 66 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 67 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 68 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 69 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 70 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 71 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 72 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 73 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 74 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 75 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 76 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 77 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 78 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 79 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 80 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 81 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 82 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 83 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 84 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 85 RK_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 86 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 87 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 88 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 89 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 90 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 91 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 92 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 93 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 94 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 95 RK_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 96 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 97 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 98 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 99 RK_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 100 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 101 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 102 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 103 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 104 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 105 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 106 }; 107 108 static const struct rk_cru_pll_rate pll_frac_rates[] = { 109 RK_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), 110 RK_PLL_RATE( 983040000, 24, 983, 1, 1, 0, 671088), 111 RK_PLL_RATE( 491520000, 24, 983, 2, 1, 0, 671088), 112 RK_PLL_RATE( 61440000, 6, 215, 7, 2, 0, 671088), 113 RK_PLL_RATE( 56448000, 12, 451, 4, 4, 0, 9797894), 114 RK_PLL_RATE( 40960000, 12, 409, 4, 5, 0, 10066329), 115 }; 116 117 static const struct rk_cru_pll_rate pll_norates[] = { 118 }; 119 120 static const struct rk_cru_arm_rate armclk_rates[] = { 121 RK_ARM_RATE(1296000000, 1), 122 RK_ARM_RATE(1200000000, 1), 123 RK_ARM_RATE(1104000000, 1), 124 RK_ARM_RATE(1008000000, 1), 125 RK_ARM_RATE( 912000000, 1), 126 RK_ARM_RATE( 816000000, 1), 127 RK_ARM_RATE( 696000000, 1), 128 RK_ARM_RATE( 600000000, 1), 129 RK_ARM_RATE( 408000000, 1), 130 RK_ARM_RATE( 312000000, 1), 131 RK_ARM_RATE( 216000000, 1), 132 RK_ARM_RATE( 96000000, 1), 133 }; 134 135 static const char * pll_parents[] = { "xin24m" }; 136 static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" }; 137 static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" }; 138 static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" }; 139 static const char * pclk_bus_pre_parents[] = { "aclk_bus_pre" }; 140 static const char * aclk_peri_pre_parents[] = { "cpll", "gpll", "hdmiphy_peri" }; 141 static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "usb480m" }; 142 static const char * phclk_peri_parents[] = { "aclk_peri_pre" }; 143 static const char * mux_hdmiphy_parents[] = { "hdmi_phy", "xin24m" }; 144 static const char * mux_usb480m_parents[] = { "usb480m_phy", "xin24m" }; 145 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 146 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 147 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 148 static const char * mux_mac2io_src_parents[] = { "clk_mac2io_src", "gmac_clkin" }; 149 static const char * mux_mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" }; 150 static const char * mux_clk_tsadc_parents[] = { "clk_24m" }; 151 static const char * mux_2plls_parents[] = { "cpll", "gpll" }; 152 static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" }; 153 static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" }; 154 static const char * pclk_gmac_parents[] = { "aclk_gmac" }; 155 static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m" }; 156 static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "xin12m" }; 157 static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "xin12m" }; 158 static const char * mux_spdif_parents[] = { "clk_spdif_div", "clk_spdif_frac", "xin12m" }; 159 static const char * mux_i2s1out_parents[] = { "clk_i2s1", "xin12m" }; 160 static const char * mux_i2s2out_parents[] = { "clk_i2s2", "xin12m" }; 161 162 static struct rk_cru_clk rk3328_cru_clks[] = { 163 RK_PLL(RK3328_PLL_APLL, "apll", pll_parents, 164 PLL_CON(0), /* con_base */ 165 0x80, /* mode_reg */ 166 __BIT(0), /* mode_mask */ 167 __BIT(4), /* lock_mask */ 168 pll_frac_rates), 169 RK_PLL(RK3328_PLL_DPLL, "dpll", pll_parents, 170 PLL_CON(8), /* con_base */ 171 0x80, /* mode_reg */ 172 __BIT(4), /* mode_mask */ 173 __BIT(3), /* lock_mask */ 174 pll_norates), 175 RK_PLL(RK3328_PLL_CPLL, "cpll", pll_parents, 176 PLL_CON(16), /* con_base */ 177 0x80, /* mode_reg */ 178 __BIT(8), /* mode_mask */ 179 __BIT(2), /* lock_mask */ 180 pll_rates), 181 RK_PLL(RK3328_PLL_GPLL, "gpll", pll_parents, 182 PLL_CON(24), /* con_base */ 183 0x80, /* mode_reg */ 184 __BIT(12), /* mode_mask */ 185 __BIT(1), /* lock_mask */ 186 pll_frac_rates), 187 RK_PLL(RK3328_PLL_NPLL, "npll", pll_parents, 188 PLL_CON(40), /* con_base */ 189 0x80, /* mode_reg */ 190 __BIT(1), /* mode_mask */ 191 __BIT(0), /* lock_mask */ 192 pll_rates), 193 194 RK_ARM(RK3328_ARMCLK, "armclk", armclk_parents, 195 CLKSEL_CON(0), /* reg */ 196 __BITS(7,6), 3, 1, /* mux_mask, mux_main, mux_alt */ 197 __BITS(4,0), /* div_mask */ 198 armclk_rates), 199 200 RK_COMPOSITE(RK3328_ACLK_BUS_PRE, "aclk_bus_pre", aclk_bus_pre_parents, 201 CLKSEL_CON(0), /* muxdiv_reg */ 202 __BITS(14,13), /* mux_mask */ 203 __BITS(12,8), /* div_mask */ 204 CLKGATE_CON(8), /* gate_reg */ 205 __BIT(0), /* gate_mask */ 206 0), 207 RK_COMPOSITE(RK3328_HCLK_BUS_PRE, "hclk_bus_pre", hclk_bus_pre_parents, 208 CLKSEL_CON(1), /* muxdiv_reg */ 209 0, /* mux_mask */ 210 __BITS(9,8), /* div_mask */ 211 CLKGATE_CON(8), /* gate_reg */ 212 __BIT(1), /* gate_mask */ 213 0), 214 RK_COMPOSITE(RK3328_PCLK_BUS_PRE, "pclk_bus_pre", pclk_bus_pre_parents, 215 CLKSEL_CON(1), /* muxdiv_reg */ 216 0, /* mux_mask */ 217 __BITS(14,12), /* div_mask */ 218 CLKGATE_CON(8), /* gate_reg */ 219 __BIT(2), /* gate_mask */ 220 0), 221 RK_COMPOSITE(RK3328_SCLK_SPI, "clk_spi", mux_2plls_parents, 222 CLKSEL_CON(24), /* muxdiv_reg */ 223 __BIT(7), /* mux_mask */ 224 __BITS(6,0), /* div_mask */ 225 CLKGATE_CON(2), /* gate_reg */ 226 __BIT(7), /* gate_mask */ 227 0), 228 RK_COMPOSITE(RK3328_SCLK_PWM, "clk_pwm", mux_2plls_parents, 229 CLKSEL_CON(24), /* muxdiv_reg */ 230 __BIT(15), /* mux_mask */ 231 __BITS(14,8), /* div_mask */ 232 CLKGATE_CON(2), /* gate_reg */ 233 __BIT(8), /* gate_mask */ 234 0), 235 RK_COMPOSITE(RK3328_ACLK_PERI_PRE, "aclk_peri_pre", aclk_peri_pre_parents, 236 CLKSEL_CON(28), /* muxdiv_reg */ 237 __BITS(7,6), /* mux_mask */ 238 __BITS(4,0), /* div_mask */ 239 0, 0, /* gate_reg, gate_mask */ 240 0), 241 RK_COMPOSITE(RK3328_PCLK_PERI, "pclk_peri", phclk_peri_parents, 242 CLKSEL_CON(29), /* muxdiv_reg */ 243 0, /* mux_mask */ 244 __BITS(1,0), /* div_mask */ 245 CLKGATE_CON(10), /* gate_reg */ 246 __BIT(2), /* gate_mask */ 247 0), 248 RK_COMPOSITE(RK3328_HCLK_PERI, "hclk_peri", phclk_peri_parents, 249 CLKSEL_CON(29), /* muxdiv_reg */ 250 0, /* mux_mask */ 251 __BITS(6,4), /* div_mask */ 252 CLKGATE_CON(10), /* gate_reg */ 253 __BIT(1), /* gate_mask */ 254 0), 255 RK_COMPOSITE(RK3328_SCLK_SDMMC, "clk_sdmmc", mmc_parents, 256 CLKSEL_CON(30), /* muxdiv_reg */ 257 __BITS(9,8), /* mux_mask */ 258 __BITS(7,0), /* div_mask */ 259 CLKGATE_CON(4), /* gate_reg */ 260 __BIT(3), /* gate_mask */ 261 RK_COMPOSITE_ROUND_DOWN), 262 RK_COMPOSITE(RK3328_SCLK_SDIO, "clk_sdio", mmc_parents, 263 CLKSEL_CON(31), /* muxdiv_reg */ 264 __BITS(9,8), /* mux_mask */ 265 __BITS(7,0), /* div_mask */ 266 CLKGATE_CON(4), /* gate_reg */ 267 __BIT(4), /* gate_mask */ 268 RK_COMPOSITE_ROUND_DOWN), 269 RK_COMPOSITE(RK3328_SCLK_EMMC, "clk_emmc", mmc_parents, 270 CLKSEL_CON(32), /* muxdiv_reg */ 271 __BITS(9,8), /* mux_mask */ 272 __BITS(7,0), /* div_mask */ 273 CLKGATE_CON(4), /* gate_reg */ 274 __BIT(5), /* gate_mask */ 275 RK_COMPOSITE_ROUND_DOWN), 276 RK_COMPOSITE(0, "clk_uart0_div", comp_uart_parents, 277 CLKSEL_CON(14), /* muxdiv_reg */ 278 __BITS(13,12), /* mux_mask */ 279 __BITS(6,0), /* div_mask */ 280 CLKGATE_CON(1), /* gate_reg */ 281 __BIT(14), /* gate_mask */ 282 0), 283 RK_COMPOSITE(0, "clk_uart1_div", comp_uart_parents, 284 CLKSEL_CON(16), /* muxdiv_reg */ 285 __BITS(13,12), /* mux_mask */ 286 __BITS(6,0), /* div_mask */ 287 CLKGATE_CON(2), /* gate_reg */ 288 __BIT(0), /* gate_mask */ 289 0), 290 RK_COMPOSITE(0, "clk_uart2_div", comp_uart_parents, 291 CLKSEL_CON(18), /* muxdiv_reg */ 292 __BITS(13,12), /* mux_mask */ 293 __BITS(6,0), /* div_mask */ 294 CLKGATE_CON(2), /* gate_reg */ 295 __BIT(2), /* gate_mask */ 296 0), 297 RK_COMPOSITE(RK3328_ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_parents, 298 CLKSEL_CON(35), /* muxdiv_reg */ 299 __BITS(7,6), /* mux_mask */ 300 __BITS(4,0), /* div_mask */ 301 CLKGATE_CON(3), /* gate_reg */ 302 __BIT(2), /* gate_mask */ 303 0), 304 RK_COMPOSITE(RK3328_PCLK_GMAC, "pclk_gmac", pclk_gmac_parents, 305 CLKSEL_CON(25), /* muxdiv_reg */ 306 0, /* mux_mask */ 307 __BITS(10,8), /* div_mask */ 308 CLKGATE_CON(9), /* gate_reg */ 309 __BIT(0), /* gate_mask */ 310 0), 311 RK_COMPOSITE(RK3328_SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_parents, 312 CLKSEL_CON(27), /* muxdiv_reg */ 313 __BIT(7), /* mux_mask */ 314 __BITS(4,0), /* div_mask */ 315 CLKGATE_CON(3), /* gate_reg */ 316 __BIT(1), /* gate_mask */ 317 0), 318 RK_COMPOSITE(RK3328_SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_parents, 319 CLKSEL_CON(27), /* muxdiv_reg */ 320 __BIT(15), /* mux_mask */ 321 __BITS(12,8), /* div_mask */ 322 CLKGATE_CON(3), /* gate_reg */ 323 __BIT(5), /* gate_mask */ 324 0), 325 RK_COMPOSITE(RK3328_SCLK_I2C0, "clk_i2c0", mux_2plls_parents, 326 CLKSEL_CON(34), /* muxdiv_reg */ 327 __BIT(7), /* mux_mask */ 328 __BITS(6,0), /* div_mask */ 329 CLKGATE_CON(2), /* gate_reg */ 330 __BIT(9), /* gate_mask */ 331 0), 332 RK_COMPOSITE(RK3328_SCLK_I2C1, "clk_i2c1", mux_2plls_parents, 333 CLKSEL_CON(34), /* muxdiv_reg */ 334 __BIT(15), /* mux_mask */ 335 __BITS(14,8), /* div_mask */ 336 CLKGATE_CON(2), /* gate_reg */ 337 __BIT(10), /* gate_mask */ 338 0), 339 RK_COMPOSITE(RK3328_SCLK_I2C2, "clk_i2c2", mux_2plls_parents, 340 CLKSEL_CON(35), /* muxdiv_reg */ 341 __BIT(7), /* mux_mask */ 342 __BITS(6,0), /* div_mask */ 343 CLKGATE_CON(2), /* gate_reg */ 344 __BIT(11), /* gate_mask */ 345 0), 346 RK_COMPOSITE(RK3328_SCLK_I2C3, "clk_i2c3", mux_2plls_parents, 347 CLKSEL_CON(35), /* muxdiv_reg */ 348 __BIT(15), /* mux_mask */ 349 __BITS(14,8), /* div_mask */ 350 CLKGATE_CON(2), /* gate_reg */ 351 __BIT(12), /* gate_mask */ 352 0), 353 RK_COMPOSITE(RK3328_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents, 354 CLKSEL_CON(22), /* muxdiv_reg */ 355 0, /* mux_mask */ 356 __BITS(9,0), /* div_mask */ 357 CLKGATE_CON(2), /* gate_reg */ 358 __BIT(6), /* gate_mask */ 359 0), 360 RK_COMPOSITE(RK3328_SCLK_CRYPTO, "clk_crypto", mux_2plls_parents, 361 CLKSEL_CON(20), /* muxdiv_reg */ 362 __BIT(7), /* mux_mask */ 363 __BITS(4,0), /* div_mask */ 364 CLKGATE_CON(2), /* gate_reg */ 365 __BIT(4), /* gate_mask */ 366 0), 367 368 RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0), 369 370 RK_GATE(0, "apll_core", "apll", CLKGATE_CON(0), 0), 371 RK_GATE(0, "dpll_core", "dpll", CLKGATE_CON(0), 1), 372 RK_GATE(0, "gpll_core", "gpll", CLKGATE_CON(0), 2), 373 RK_GATE(0, "npll_core", "npll", CLKGATE_CON(0), 12), 374 RK_GATE(0, "gpll_peri", "gpll", CLKGATE_CON(4), 0), 375 RK_GATE(0, "cpll_peri", "cpll", CLKGATE_CON(4), 1), 376 RK_GATE(0, "hdmiphy_peri", "hdmiphy", CLKGATE_CON(4), 2), 377 RK_GATE(0, "pclk_bus", "pclk_bus_pre", CLKGATE_CON(8), 3), 378 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLKGATE_CON(8), 4), 379 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLKGATE_CON(10), 0), 380 RK_GATE(RK3328_PCLK_I2C0, "pclk_i2c0", "pclk_bus", CLKGATE_CON(15), 10), 381 RK_GATE(RK3328_PCLK_I2C1, "pclk_i2c1", "pclk_bus", CLKGATE_CON(16), 0), 382 RK_GATE(RK3328_PCLK_I2C2, "pclk_i2c2", "pclk_bus", CLKGATE_CON(16), 1), 383 RK_GATE(RK3328_PCLK_I2C3, "pclk_i2c3", "pclk_bus", CLKGATE_CON(16), 2), 384 RK_GATE(RK3328_PCLK_SPI, "pclk_spi", "pclk_bus", CLKGATE_CON(16), 5), 385 RK_GATE(RK3328_PCLK_PWM, "pclk_rk_pwm", "pclk_bus", CLKGATE_CON(16), 6), 386 RK_GATE(RK3328_PCLK_GPIO0, "pclk_gpio0", "pclk_bus", CLKGATE_CON(16), 7), 387 RK_GATE(RK3328_PCLK_GPIO1, "pclk_gpio1", "pclk_bus", CLKGATE_CON(16), 8), 388 RK_GATE(RK3328_PCLK_GPIO2, "pclk_gpio2", "pclk_bus", CLKGATE_CON(16), 9), 389 RK_GATE(RK3328_PCLK_GPIO3, "pclk_gpio3", "pclk_bus", CLKGATE_CON(16), 10), 390 RK_GATE(RK3328_PCLK_UART0, "pclk_uart0", "pclk_bus", CLKGATE_CON(16), 11), 391 RK_GATE(RK3328_PCLK_UART1, "pclk_uart1", "pclk_bus", CLKGATE_CON(16), 12), 392 RK_GATE(RK3328_PCLK_UART2, "pclk_uart2", "pclk_bus", CLKGATE_CON(16), 13), 393 RK_GATE(RK3328_PCLK_TSADC, "pclk_tsadc", "pclk_bus", CLKGATE_CON(16), 14), 394 RK_GATE(RK3328_SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", CLKGATE_CON(9), 7), 395 RK_GATE(RK3328_SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", CLKGATE_CON(9), 4), 396 RK_GATE(RK3328_SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", CLKGATE_CON(9), 5), 397 RK_GATE(RK3328_SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", CLKGATE_CON(9), 6), 398 RK_GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLKGATE_CON(15), 15), 399 RK_GATE(RK3328_ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", CLKGATE_CON(19), 4), 400 RK_GATE(RK3328_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", CLKGATE_CON(19), 0), 401 RK_GATE(RK3328_HCLK_SDIO, "hclk_sdio", "hclk_peri", CLKGATE_CON(19), 1), 402 RK_GATE(RK3328_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(19), 2), 403 RK_GATE(RK3328_HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", CLKGATE_CON(19), 15), 404 RK_GATE(RK3328_HCLK_HOST0, "hclk_host0", "hclk_peri", CLKGATE_CON(19), 6), 405 RK_GATE(RK3328_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLKGATE_CON(19), 7), 406 RK_GATE(RK3328_HCLK_OTG, "hclk_otg", "hclk_peri", CLKGATE_CON(19), 8), 407 RK_GATE(RK3328_HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", CLKGATE_CON(19), 9), 408 RK_GATE(RK3328_ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", CLKGATE_CON(26), 2), 409 RK_GATE(RK3328_PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", CLKGATE_CON(26), 3), 410 RK_GATE(0, "aclk_gmac_niu", "aclk_gmac", CLKGATE_CON(26), 4), 411 RK_GATE(0, "pclk_gmac_niu", "pclk_gmac", CLKGATE_CON(26), 5), 412 413 RK_MUX(RK3328_HDMIPHY, "hdmiphy", mux_hdmiphy_parents, MISC_CON, __BIT(13)), 414 RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, MISC_CON, __BIT(15)), 415 RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, CLKSEL_CON(14), __BITS(9,8)), 416 RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, CLKSEL_CON(16), __BITS(9,8)), 417 RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, CLKSEL_CON(18), __BITS(9,8)), 418 RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, GRF_MAC_CON1, __BIT(10)), 419 RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, GRF_SOC_CON4, __BIT(14)), 420 421 /* I2S */ 422 RK_COMPOSITE(0, "clk_i2s0_div", mux_2plls_parents, 423 CLKSEL_CON(6), /* muxdiv_reg */ 424 __BIT(15), /* mux_mask */ 425 __BITS(6,0), /* div_mask */ 426 CLKGATE_CON(1), /* gate_reg */ 427 __BIT(1), /* gate_mask */ 428 0), 429 RK_COMPOSITE(0, "clk_i2s1_div", mux_2plls_parents, 430 CLKSEL_CON(8), /* muxdiv_reg */ 431 __BIT(15), /* mux_mask */ 432 __BITS(6,0), /* div_mask */ 433 CLKGATE_CON(1), /* gate_reg */ 434 __BIT(4), /* gate_mask */ 435 0), 436 RK_COMPOSITE(0, "clk_i2s2_div", mux_2plls_parents, 437 CLKSEL_CON(10), /* muxdiv_reg */ 438 __BIT(15), /* mux_mask */ 439 __BITS(6,0), /* div_mask */ 440 CLKGATE_CON(1), /* gate_reg */ 441 __BIT(8), /* gate_mask */ 442 0), 443 RK_COMPOSITE(0, "clk_spdif_div", mux_2plls_parents, 444 CLKSEL_CON(12), /* muxdiv_reg */ 445 __BIT(15), /* mux_mask */ 446 __BITS(6,0), /* div_mask */ 447 CLKGATE_CON(1), /* gate_reg */ 448 __BIT(12), /* gate_mask */ 449 0), 450 RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div", 451 CLKSEL_CON(7), /* frac_reg */ 452 RK_COMPOSITE_SET_RATE_PARENT), 453 RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div", 454 CLKSEL_CON(9), /* frac_reg */ 455 RK_COMPOSITE_SET_RATE_PARENT), 456 RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div", 457 CLKSEL_CON(11), /* frac_reg */ 458 RK_COMPOSITE_SET_RATE_PARENT), 459 RK_COMPOSITE_FRAC(0, "clk_spdif_frac", "clk_spdif_div", 460 CLKSEL_CON(13), /* frac_reg */ 461 RK_COMPOSITE_SET_RATE_PARENT), 462 RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(6), __BITS(9,8)), 463 RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(8), __BITS(9,8)), 464 RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(10), __BITS(9,8)), 465 RK_MUX(0, "clk_spdif_mux", mux_spdif_parents, CLKSEL_CON(10), __BITS(9,8)), 466 RK_GATE(RK3328_SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(1), 3), 467 RK_GATE(RK3328_SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(1), 6), 468 RK_GATE(RK3328_SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(1), 10), 469 RK_GATE(RK3328_SCLK_SPDIF, "clk_spdif", "clk_spdif_mux", CLKGATE_CON(1), 12), 470 RK_GATE(RK3328_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_bus_pre", CLKGATE_CON(15), 3), 471 RK_GATE(RK3328_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_bus_pre", CLKGATE_CON(15), 4), 472 RK_GATE(RK3328_HCLK_I2S2_2CH, "hclk_i2s2", "hclk_bus_pre", CLKGATE_CON(15), 5), 473 RK_GATE(RK3328_HCLK_SPDIF_8CH, "hclk_spdif", "hclk_bus_pre", CLKGATE_CON(15), 6), 474 RK_GATE(RK3328_HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", CLKGATE_CON(15), 7), 475 RK_GATE(RK3328_HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", CLKGATE_CON(15), 8), 476 RK_COMPOSITE(RK3328_SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_parents, 477 CLKSEL_CON(8), /* muxdiv_reg */ 478 __BIT(12), /* mux_mask */ 479 0, /* div_mask */ 480 CLKGATE_CON(7), /* gate_reg */ 481 __BIT(12), /* gate_mask */ 482 RK_COMPOSITE_SET_RATE_PARENT), 483 RK_COMPOSITE(RK3328_SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_parents, 484 CLKSEL_CON(10), /* muxdiv_reg */ 485 __BIT(12), /* mux_mask */ 486 0, /* div_mask */ 487 CLKGATE_CON(11), /* gate_reg */ 488 __BIT(12), /* gate_mask */ 489 RK_COMPOSITE_SET_RATE_PARENT), 490 }; 491 492 static int 493 rk3328_cru_match(device_t parent, cfdata_t cf, void *aux) 494 { 495 struct fdt_attach_args * const faa = aux; 496 497 return of_compatible_match(faa->faa_phandle, compat_data); 498 } 499 500 static void 501 rk3328_cru_attach(device_t parent, device_t self, void *aux) 502 { 503 struct rk_cru_softc * const sc = device_private(self); 504 struct fdt_attach_args * const faa = aux; 505 506 sc->sc_dev = self; 507 sc->sc_phandle = faa->faa_phandle; 508 sc->sc_bst = faa->faa_bst; 509 510 sc->sc_clks = rk3328_cru_clks; 511 sc->sc_nclks = __arraycount(rk3328_cru_clks); 512 513 sc->sc_grf_soc_status = 0x0480; 514 sc->sc_softrst_base = SOFTRST_CON(0); 515 516 if (rk_cru_attach(sc) != 0) 517 return; 518 519 aprint_naive("\n"); 520 aprint_normal(": RK3328 CRU\n"); 521 522 rk_cru_print(sc); 523 } 524
Indexes created Sat Sep 20 22:09:52 GMT 2025