Lines Matching defs:CLKGATE_CON
45 #define CLKGATE_CON(n) (0x0300 + (n) * 4)
439 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0),
440 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1),
441 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2),
442 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3),
451 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0),
452 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1),
453 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2),
454 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3),
466 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0),
467 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1),
472 CLKGATE_CON(7), /* gate_reg */
478 CLKGATE_CON(7), /* gate_reg */
484 CLKGATE_CON(7), /* gate_reg */
491 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0),
492 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1),
501 CLKGATE_CON(8), /* gate_reg */
508 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0),
509 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1),
514 CLKGATE_CON(5), /* gate_reg */
520 CLKGATE_CON(5), /* gate_reg */
526 CLKGATE_CON(5), /* gate_reg */
533 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0),
534 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1),
535 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2),
536 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3),
541 CLKGATE_CON(2), /* gate_reg */
544 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2),
553 CLKGATE_CON(12), /* gate_reg */
564 CLKGATE_CON(3), /* gate_reg */
576 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3),
577 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4),
578 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5),
588 CLKGATE_CON(9), /* gate_reg */
594 CLKGATE_CON(9), /* gate_reg */
600 CLKGATE_CON(9), /* gate_reg */
606 CLKGATE_CON(9), /* gate_reg */
613 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0),
614 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1),
615 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2),
616 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3),
625 CLKGATE_CON(12), /* gate_reg */
632 CLKGATE_CON(6), /* gate_reg */
639 CLKGATE_CON(6), /* gate_reg */
642 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8),
643 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4),
652 CLKGATE_CON(6), /* gate_reg */
655 RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13),
656 RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12),
662 RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8),
663 RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9),
664 RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10),
673 CLKGATE_CON(5), /* gate_reg */
677 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6),
678 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7),
679 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8),
680 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9),
681 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8),
682 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9),
687 CLKGATE_CON(6), /* gate_reg */
690 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0),
694 CLKGATE_CON(6), /* gate_reg */
697 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2),
702 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5),
703 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6),
704 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7),
705 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8),
706 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5),
707 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6),
712 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1),
713 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2),
718 CLKGATE_CON(12), /* gate_reg */
725 CLKGATE_CON(12), /* gate_reg */
732 CLKGATE_CON(12), /* gate_reg */
735 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1),
736 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2),
737 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3),
738 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4),
745 CLKGATE_CON(13), /* gate_reg */
752 CLKGATE_CON(13), /* gate_reg */
759 CLKGATE_CON(13), /* gate_reg */
766 CLKGATE_CON(13), /* gate_reg */
777 CLKGATE_CON(10), /* gate_reg */
784 CLKGATE_CON(10), /* gate_reg */
791 CLKGATE_CON(10), /* gate_reg */
798 CLKGATE_CON(10), /* gate_reg */
805 CLKGATE_CON(10), /* gate_reg */
812 CLKGATE_CON(10), /* gate_reg */
815 RK_GATE(RK3399_PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", CLKGATE_CON(22), 5),
816 RK_GATE(RK3399_PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", CLKGATE_CON(22), 6),
817 RK_GATE(RK3399_PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", CLKGATE_CON(22), 7),
818 RK_GATE(RK3399_PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", CLKGATE_CON(22), 8),
819 RK_GATE(RK3399_PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", CLKGATE_CON(22), 9),
820 RK_GATE(RK3399_PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", CLKGATE_CON(22), 10),
829 CLKGATE_CON(9), /* gate_reg */
836 CLKGATE_CON(9), /* gate_reg */
843 CLKGATE_CON(9), /* gate_reg */
850 CLKGATE_CON(9), /* gate_reg */
857 CLKGATE_CON(13), /* gate_reg */
860 RK_GATE(RK3399_PCLK_SPI0, "pclk_rkspi0", "pclk_perilp1", CLKGATE_CON(23), 10),
861 RK_GATE(RK3399_PCLK_SPI1, "pclk_rkspi1", "pclk_perilp1", CLKGATE_CON(23), 11),
862 RK_GATE(RK3399_PCLK_SPI2, "pclk_rkspi2", "pclk_perilp1", CLKGATE_CON(23), 12),
863 RK_GATE(RK3399_PCLK_SPI4, "pclk_rkspi4", "pclk_perilp1", CLKGATE_CON(23), 13),
864 RK_GATE(RK3399_PCLK_SPI5, "pclk_rkspi5", "hclk_perilp1", CLKGATE_CON(34), 5),
870 RK_GATE(RK3399_ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLKGATE_CON(20), 2),
871 RK_GATE(RK3399_ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLKGATE_CON(20), 10),
872 RK_GATE(RK3399_PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLKGATE_CON(20), 11),
877 CLKGATE_CON(6), /* gate_reg */
883 CLKGATE_CON(12), /* gate_reg */
891 CLKGATE_CON(6), /* gate_reg */
901 CLKGATE_CON(7), /* gate_reg */
908 CLKGATE_CON(8), /* gate_reg */
911 RK_GATE(RK3399_HCLK_M_CRYPTO0, "hclk_m_crypto0", "pclk_perilp0", CLKGATE_CON(24), 5),
912 RK_GATE(RK3399_HCLK_S_CRYPTO0, "hclk_s_crypto0", "pclk_perilp0", CLKGATE_CON(24), 6),
913 RK_GATE(RK3399_HCLK_M_CRYPTO1, "hclk_m_crypto1", "pclk_perilp0", CLKGATE_CON(24), 14),
914 RK_GATE(RK3399_HCLK_S_CRYPTO1, "hclk_s_crypto1", "pclk_perilp0", CLKGATE_CON(24), 15),
915 RK_GATE(RK3399_ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "pclk_perilp", CLKGATE_CON(25), 6),
922 CLKGATE_CON(9), /* gate_reg */
925 RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13),
932 CLKGATE_CON(10), /* gate_reg */
938 CLKGATE_CON(10), /* gate_reg */
945 CLKGATE_CON(10), /* gate_reg */
948 RK_GATE(RK3399_ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLKGATE_CON(28), 3),
949 RK_GATE(RK3399_HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLKGATE_CON(28), 2),
960 CLKGATE_CON(10), /* gate_reg */
966 CLKGATE_CON(10), /* gate_reg */
973 CLKGATE_CON(10), /* gate_reg */
976 RK_GATE(RK3399_ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLKGATE_CON(28), 7),
977 RK_GATE(RK3399_HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLKGATE_CON(28), 6),
988 CLKGATE_CON(11), /* gate_reg */
994 CLKGATE_CON(11), /* gate_reg */
997 RK_GATE(RK3399_PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLKGATE_CON(29), 12),
1004 CLKGATE_CON(11), /* gate_reg */
1010 CLKGATE_CON(11), /* gate_reg */
1017 CLKGATE_CON(11), /* gate_reg */
1020 RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6),
1021 RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6),
1028 CLKGATE_CON(8), /* gate_reg */
1035 CLKGATE_CON(8), /* gate_reg */
1042 CLKGATE_CON(8), /* gate_reg */
1057 RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5),
1058 RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8),
1059 RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11),
1060 RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0),
1061 RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1),
1062 RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2),
1068 CLKGATE_CON(8), /* gate_reg */
1077 CLKGATE_CON(11), /* gate_reg */
1080 RK_GATE(RK3399_PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLKGATE_CON(32), 12),
1081 RK_GATE(RK3399_PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLKGATE_CON(32), 13),
1087 CLKGATE_CON(11), /* gate_reg */
1090 RK_GATE(RK3399_PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLKGATE_CON(29), 7),
1096 CLKGATE_CON(13), /* gate_reg */
1099 RK_GATE(RK3399_ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLKGATE_CON(30), 8),
1100 RK_GATE(RK3399_ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", CLKGATE_CON(30), 10),
1101 RK_GATE(RK3399_ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", CLKGATE_CON(30), 11),
1102 RK_GATE(RK3399_SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", CLKGATE_CON(13), 1),
1103 RK_GATE(0, "aclk_gpu_pll_src", "xin24m", CLKGATE_CON(13), 0),
Indexes created Thu Oct 02 14:10:14 GMT 2025