| History log of /src/sys/arch/arm/rockchip/rk3399_cru.c |
| Revision | | Date | Author | Comments |
| 1.27 |
| 03-Jun-2025 |
rjs | Add GPU clocks.
|
| 1.26 |
| 03-Jun-2025 |
rjs | Add driver for Rockchip USB-C PHY, mostly from OpenBSD.
Only implements USB3 for now, not DP.
|
| 1.25 |
| 23-Aug-2022 |
ryo | branches: 1.25.10;
- change struct rk_cru_arm and RK_CPU macros to allow mux and div registers to be specified independently.
Allow more div-regs to be specified in the future.
- commonize RK*_PLL() macro.
|
| 1.24 |
| 23-Aug-2022 |
ryo | Make .reg1 and .reg2 of struct rk_cru_cpu_rate into array, and change the type of those to bus_size_t and uint32_t.
Array size may increase in the future.
|
| 1.23 |
| 12-Nov-2021 |
jmcneill | arm: rockchip: Add support for RK3288 SoC.
The Rockchip RK3288 is a quad core Cortex-A17 SoC.
|
| 1.22 |
| 20-May-2021 |
msaitoh | Fix signed integer overflow found by kUBSan. OK'd by jmcneill.
The output was:
UBSan: Undefined Behavior in ../../../../arch/arm/rockchip/rk3399_cru.c:
284:13, signed integer overflow: 594000000 - -2086967296 cannot be
represented in type 'int'
|
| 1.21 |
| 27-Jan-2021 |
thorpej | branches: 1.21.4; 1.21.6;
Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().
Standardize on of_compatible_match() for driver matching, and adapt
all call sites.
|
| 1.20 |
| 17-May-2020 |
riastradh | branches: 1.20.2;
Rockchip crypto engine RNG driver.
As found on the rk3288 and rk3399. This driver only supports the
TRNG, not the rest of the crypto engine, although it uses the AES unit
to do a self-test at attach time to verify that the engine works.
There seem to be two versions of the Rockchip crypto engine, v1 and
v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll
clumsily call it `rkv1crypto' instead to leave room for `rkv2crypto'
later on.
The crypto binding derived from the Rockchip BSP Linux kernel, in the
location it appears on the rk3399, is in rk3399-crypto.dtsi, since
there doesn't seem to be a better place to put it at the moment among
this twisty maze of inclusions, all different.
|
| 1.19 |
| 04-Jan-2020 |
jmcneill | Add 2000 MHz to available armclkb rates
|
| 1.18 |
| 18-Dec-2019 |
jakllsch | rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac.
The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div.
vpll is apparently used directly as a pixel clock source for the
HDMI PHY, and we don't want the other VOP's dclk changing out from
under it because we can't handle finding a replacement clock source
with the right rate yet.
gpll happens to run at 594MHz, which works well as a basis for pixel
clocks.
Linux suggests that the source clock of the fractional divider needs
to be more than twenty times greater than the resulting clock (or some
intermediate clock?) for output stability. This may not be the case
with 594MHz and the common pixel clocks I see used by displays in my
area of the wild, but it works for now.
|
| 1.17 |
| 17-Dec-2019 |
jakllsch | rk3399_cru: implement dclk_vop0_frac and dclk_vop1_frac
|
| 1.16 |
| 29-Nov-2019 |
jakllsch | add RK3399 DisplayPort clocks
|
| 1.15 |
| 29-Nov-2019 |
jakllsch | add RK3399 eDP clocks
|
| 1.14 |
| 29-Nov-2019 |
jakllsch | fix copy/paste error in mux_pll_src_cpll_gpll_ppll_parents[]
|
| 1.13 |
| 16-Nov-2019 |
jmcneill | Add support for I2S clocks.
|
| 1.12 |
| 10-Nov-2019 |
jmcneill | Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.
|
| 1.11 |
| 09-Nov-2019 |
jmcneill | Add HDMI and VOP clocks
|
| 1.10 |
| 19-Oct-2019 |
tnn | rk3399: add definition for the watchdog timer clock gate
The watchdog timer clock gate is a bit special because it's a secure
gate that can only be accessed from EL3. We still need a dummy gate
definition for it so that dwcwdt(4) can infer the frequency via the
parent clock. The gate is enabled by default by U-Boot.
|
| 1.9 |
| 04-Aug-2019 |
tnn | rk3399_cru: add definitions for SPI clocks
|
| 1.8 |
| 09-Jun-2019 |
jmcneill | branches: 1.8.2; 1.8.4;
Init bpll in a way that brings the big cluster's PLL out of "slow mode".
While here, fix a few typos in the cpul's rate table.
|
| 1.7 |
| 26-Apr-2019 |
mrg | implement TSADC driver for rockchip RK3328 and RK3399. so far, only
tested on RK3399 but the RK3328 looks mostly the same and has a good
chance of working too.
add clock entries for "clk_tsadc" and "pclk_tsadc" to cru.
exports "CPU" and "GPU" temp sensors. these currently limited to 5
degC resolution but can be reduced to sub 1 degC resolution with some
interpolation.
todo list:
- handle setting various temp values
- add interpolation between the 5degC intervals in sample data
- handle DT trips/temp value defaults
- interrupts aren't triggered (test by lowering warn/crit values),
and once they work, make the interrupt do something
- test on RK3328, and port to other rockchips (will require moving
some part into per-chipset sections, such as code<->temp tables)
thanks to jmcneill for help.
|
| 1.6 |
| 13-Mar-2019 |
jmcneill | Fix aclk_emmc register offset, set RK_COMPOSITE_ROUND_DOWN for SD/EMMC clocks, and add a few more emmc clock nodes
|
| 1.5 |
| 10-Mar-2019 |
jmcneill | Add eMMC clocks
|
| 1.4 |
| 11-Nov-2018 |
jakllsch | Add clock information for RK3399 PCIe
|
| 1.3 |
| 01-Sep-2018 |
jmcneill | branches: 1.3.2;
Add support for RK3399 CPU clocks.
|
| 1.2 |
| 12-Aug-2018 |
jmcneill | Add I2C clocks
|
| 1.1 |
| 12-Aug-2018 |
jmcneill | Add support for Rockchip RK3399 SoC.
|
| 1.3.2.3 |
| 26-Nov-2018 |
pgoyette | Sync with HEAD, resolve a couple of conflicts
|
| 1.3.2.2 |
| 06-Sep-2018 |
pgoyette | Sync with HEAD
Resolve a couple of conflicts (result of the uimin/uimax changes)
|
| 1.3.2.1 |
| 01-Sep-2018 |
pgoyette | file rk3399_cru.c was added on branch pgoyette-compat on 2018-09-06 06:55:27 +0000
|
| 1.8.4.4 |
| 18-May-2020 |
martin | Pull up following revision(s) (requested by riastradh in ticket #913):
sys/arch/arm/dts/rk3399-crypto.dtsi: revision 1.1
sys/arch/arm/rockchip/rk_v1crypto.c: revision 1.1
sys/arch/arm/rockchip/rk_v1crypto.c: revision 1.2 (plus patch)
sys/arch/arm/rockchip/rk_v1crypto.h: revision 1.1
sys/arch/arm/dts/rk3399-pinebook-pro.dts: revision 1.3
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.20
sys/arch/evbarm/conf/GENERIC64: revision 1.158
sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.11
sys/arch/arm/rockchip/files.rockchip: revision 1.24
Rockchip crypto engine RNG driver.
As found on the rk3288 and rk3399. This driver only supports the
TRNG, not the rest of the crypto engine, although it uses the AES unit
to do a self-test at attach time to verify that the engine works.
There seem to be two versions of the Rockchip crypto engine, v1 and
v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll
clumsily call it `rkv1crypto' instead to leave room for `rkv2crypto'
later on.
The crypto binding derived from the Rockchip BSP Linux kernel, in the
location it appears on the rk3399, is in rk3399-crypto.dtsi, since
there doesn't seem to be a better place to put it at the moment among
this twisty maze of inclusions, all different.
Use rnd_add_data_sync from the callback.
(Doesn't make a difference in HEAD but this is the stated API
contract and it matters if we want to pull this up.)
Prime the pool on attach.
|
| 1.8.4.3 |
| 21-Jan-2020 |
martin | Pull up following revision(s) (requested by mrg in ticket #616):
sys/dev/ic/anx_dp.c: revision 1.2
sys/arch/evbarm/conf/GENERIC64: revision 1.126
sys/dev/ic/anx_dp.h: revision 1.1
sys/arch/evbarm/conf/GENERIC64: revision 1.128
sys/dev/ic/anx_dp.h: revision 1.2
sys/dev/fdt/dwcmmc_fdt.c: revision 1.9
sys/dev/i2c/cwfg.c: revision 1.1
sys/conf/files: revision 1.1247
sys/dev/fdt/pwm_backlight.c: revision 1.5
sys/dev/fdt/pwm_backlight.c: revision 1.6
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.14
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.15
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.16
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.17
sys/dev/ic/dwc_mmc.c: revision 1.20
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.18
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.19
sys/dev/usb/usbdevs: revision 1.775
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.4
sys/dev/fdt/simple_amplifier.c: revision 1.1
sys/dev/i2c/files.i2c: revision 1.105
sys/arch/evbarm/conf/GENERIC64: revision 1.117
sys/arch/evbarm/conf/GENERIC64: revision 1.118
sys/dev/i2c/files.i2c: revision 1.107
sys/dev/fdt/files.fdt: revision 1.49
sys/arch/arm/rockchip/rk_anxdp.c: revision 1.1
sys/dev/ic/dwc_mmc_var.h: revision 1.9
sys/dev/i2c/rkpmic.c: revision 1.4
sys/arch/arm/rockchip/rk_anxdp.c: revision 1.2
sys/dev/i2c/rkpmic.c: revision 1.5
sys/dev/i2c/rkpmic.c: revision 1.6
sys/arch/arm/rockchip/rk_vop.c: revision 1.4
sys/arch/arm/rockchip/rk_vop.c: revision 1.5
sys/dev/i2c/rkpmic.c: revision 1.8
sys/arch/arm/dts/rk3399-pinebook-pro.dts: revision 1.1
sys/dev/usb/ums.c: revision 1.96 (via patch)
sys/arch/arm/rockchip/rk_pwm.c: revision 1.3
sys/arch/arm/dts/rk3399-pinebook-pro.dts: revision 1.2
sys/dev/i2c/es8316ac.c: revision 1.1
sys/dev/fdt/dwcmmc_fdt.c: revision 1.10
sys/dev/i2c/es8316ac.c: revision 1.2
sys/dev/fdt/fdt_panel.c: revision 1.1
sys/dev/ic/dwc_mmc.c: revision 1.18
sys/dev/fdt/fdt_panel.c: revision 1.2
sys/dev/ic/dwc_mmc.c: revision 1.19
sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.10
sys/dev/fdt/fdt_port.c: revision 1.5
sys/dev/ic/dwc_mmc_var.h: revision 1.10
sys/dev/fdt/fdt_port.c: revision 1.6
sys/arch/evbarm/conf/GENERIC64: revision 1.122
sys/dev/ic/dwc_mmc_var.h: revision 1.11
sys/dev/fdt/files.fdt: revision 1.50
sys/arch/evbarm/conf/GENERIC64: revision 1.123
sys/arch/arm/rockchip/rk_i2s.c: revision 1.2
sys/arch/arm/rockchip/files.rockchip: revision 1.23
sys/arch/evbarm/conf/GENERIC64: revision 1.124
sys/dev/ic/anx_dp.c: revision 1.1
rkpmic: add RTC support; register w/ todr(9)
rkpmic: correct delay
Add support for SDIO interrupts.
fix copy/paste error in mux_pll_src_cpll_gpll_ppll_parents[]
add RK3399 eDP clocks
add RK3399 DisplayPort clocks
style fix/KNF
rk3399_cru: implement dclk_vop0_frac and dclk_vop1_frac
Move drm_encoder from rkvop(4) to the SoC-layer output pipe drivers (rk_dwhdmi).
rkvop: set stride using virtual framebuffer width instead of display mode
rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac.
The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div.
vpll is apparently used directly as a pixel clock source for the
HDMI PHY, and we don't want the other VOP's dclk changing out from
under it because we can't handle finding a replacement clock source
with the right rate yet.
gpll happens to run at 594MHz, which works well as a basis for pixel
clocks.
Linux suggests that the source clock of the fractional divider needs
to be more than twenty times greater than the resulting clock (or some
intermediate clock?) for output stability. This may not be the case
with 594MHz and the common pixel clocks I see used by displays in my
area of the wild, but it works for now.
add Analogix DisplayPort core driver
add Rockchip (RK3399) glue for Analogix DisplayPort core
add anxdp(4)
Add another panel@fdt driver, this time for DRM-style panels.
To do: migrate away from other panel driver.
enable panel at fdt drivers
paper over the rkpwm get_conf function that otherwise doesn't seem to
let things work
add template bits for optional eDP panel on RockPro64
Abort panel driver attach if required regulator is missing.
Add clk provider
Add Pinebook Pro dts, from Manjaro Linux.
https://gitlab.manjaro.org/tsys/linux-pinebook-pro/blob/877ca0e7283596f37845de50dc36bff5b88b91e1/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+ rk3399-pinebook-pro.dts
Attach mmcpwrseq resource earlier
dwcmmc improvements:
- Use mmcpwrseq resources if available
- Only set 4- or 8-bit mode if specified in the dt properties
- Add quirk for implementations with inverted power enable logic
- Support switching signal voltage between 1.8V and 3.3V
- Fix a clock divider issue on Rockchip SoCs
Fix performance regression with previous
Quiet chatty printfs
No need to print all supported levels at attach, print the range and total number of steps
Disable SPI for now (rkspi driver hangs at boot)
Add driver for simple-audio-amplifier binding
Add driver for Everest Semi ES8316 Low Power Audio CODEC
add es8316, simpleamp
Avoid sleeping while the audio intr lock is held.
If the rockchip,system-power-controller property is present, try to power off with the PMIC
Add HAILUCK keyboard (product 1e)
Add a quirk for the HAILUCK USB keyboard / touchpad device with product 1e.
The keyboard does not function properly unless the touchpad's intr endpoint
is active.
Add driver for CellWise CW2015 Fuel Gauge IC.
add cwfg
Emit PMFE_DISPLAY_{ON,OFF} events in response to DPMS requests.
If the backlight node does not have an enable gpio, set the lowest duty
cycle to turn the display off instead.
Attach psci as early as possible. This allows other power controllers to
register their own poweroff / reset callbacks with a higher preference.
Add 2000 MHz to available armclkb rates
Remove debug printfs
|
| 1.8.4.2 |
| 20-Nov-2019 |
martin | Pull up following revision(s) (requested by tnn in ticket #458):
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.9
sys/arch/arm/rockchip/rk_spi.c: revision 1.1
sys/arch/evbarm/conf/GENERIC64: revision 1.104
sys/arch/arm/rockchip/files.rockchip: revision 1.20
rk3399_cru: add definitions for SPI clocks
rk_spi: Rockchip SPI driver
Match only on RK3399 for now, but should work on RK3328 as well with
the proper CRU support. If you can, please test and enable for RK3328.
rkspi* at fdt?
|
| 1.8.4.1 |
| 16-Nov-2019 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #427):
sys/dev/ic/dw_hdmi_phy.c: revision 1.2
sys/dev/ic/dw_hdmi.c: revision 1.4
sys/dev/fdt/ausoc.c: revision 1.5
sys/dev/ic/dw_hdmi.h: revision 1.2
sys/dev/ic/dw_hdmi.h: revision 1.3
sys/dev/ic/dw_hdmi.h: revision 1.4
sys/conf/files: revision 1.1242
sys/dev/fdt/fdtvar.h: revision 1.57
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.11
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.12
sys/arch/arm/rockchip/rk3399_cru.c: revision 1.13
sys/arch/evbarm/conf/GENERIC64: revision 1.110
sys/arch/arm/rockchip/rk_drm.c: revision 1.1
sys/arch/arm/rockchip/rk_drm.c: revision 1.2
sys/arch/evbarm/conf/GENERIC64: revision 1.112
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.1
sys/dev/fdt/fdt_clock.c: revision 1.10
sys/arch/evbarm/conf/GENERIC64: revision 1.113
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.2
sys/arch/arm/rockchip/rk_drm.h: revision 1.1
sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.3
sys/arch/arm/rockchip/rk_fb.c: revision 1.1
sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.9
sys/arch/arm/rockchip/rk_vop.c: revision 1.1
sys/arch/arm/rockchip/rk_vop.c: revision 1.2
sys/arch/arm/rockchip/rk_i2c.c: revision 1.6
sys/arch/arm/rockchip/rk_cru.h: revision 1.6
sys/arch/arm/rockchip/rk_cru.h: revision 1.7
sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.4
sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.5
sys/arch/arm/rockchip/files.rockchip: revision 1.21
sys/arch/arm/rockchip/rk_i2s.c: revision 1.1
sys/arch/arm/rockchip/files.rockchip: revision 1.22
sys/dev/ic/dw_hdmi.c: revision 1.2
sys/dev/ic/dw_hdmi_phy.c: revision 1.1
sys/dev/ic/dw_hdmi.c: revision 1.3
Support reads of more than 32 bytes in a single xfer.
Add support for internal DesignWare HDMI PHYs
Add fdtbus_clock_enable and fdtbus_clock_enable_index shortcuts
Add HDMI and VOP clocks
WIP display driver for Rockchip RK3399
Add (commented out) Rockchip display support
Select the correct MPLL and PHY settings for the requested pixel clock
Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.
Fix typo in phy config table
Fix a few swapped fields
Remove debug output
Enable Rockchip display support
Set sysclk rate at set_format time, so the link set_format callback can read the new sysclk
Add I2S audio input support.
Add software volume controls.
Add support for I2S clocks.
Add driver for Rockchip I2S/PCM controller.
Enable HDMI audio on ROCKPro64
Add rki2s
Add audio support
|
| 1.8.2.3 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.8.2.2 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.8.2.1 |
| 09-Jun-2019 |
christos | file rk3399_cru.c was added on branch phil-wifi on 2019-06-10 22:05:55 +0000
|
| 1.20.2.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.21.6.1 |
| 31-May-2021 |
cjep | sync with head
|
| 1.21.4.1 |
| 17-Jun-2021 |
thorpej | Sync w/ HEAD.
|
| 1.25.10.1 |
| 02-Aug-2025 |
perseant | Sync with HEAD
|
