Cross Reference: /src/sys/arch/arm/rockchip/rk3399

Lines Matching refs:pll
236 	struct rk_cru_pll *pll = &clk->u.pll;
251 	const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
252 	const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
253 	const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
254 	const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
279 	struct rk_cru_pll *pll = &clk->u.pll;
286 	if (pll->rates == NULL || rate == 0)
290 	for (int i = 0; i < pll->nrates; i++) {
293 		if (rate > pll->rates[i].rate)
294 			diff = rate - pll->rates[i].rate;
296 			diff = pll->rates[i].rate - rate;
298 			pll_rate = &pll->rates[i];
304 	CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
306 	CRU_WRITE(sc, pll->con_base + PLL_CON0,
309 	CRU_WRITE(sc, pll->con_base + PLL_CON1,
315 	val = CRU_READ(sc, pll->con_base + PLL_CON2);
318 	CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
321 	CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
324 		if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask)
333 	/* Set PLL work mode to normal */
335 	CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
346                 .u.pll.parents = (_parents),                    \
347                 .u.pll.nparents = __arraycount(_parents),       \
348                 .u.pll.con_base = (_con_base),                  \
349                 .u.pll.mode_reg = (_mode_reg),                  \
350                 .u.pll.mode_mask = (_mode_mask),                \
351                 .u.pll.lock_mask = (_lock_mask),                \
352                 .u.pll.rates = (_rates),                        \
353                 .u.pll.nrates = __arraycount(_rates),           \
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