Lines Matching defs:CLK_DIV
311 #define CLK_DIV(_name, _parent, _reg, _bits) { \
497 CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)),
498 CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),
499 CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),
501 CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)),
502 CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)),
503 CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)),
504 CLK_DIV
505 CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),
506 CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)),
507 CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)),
508 CLK_DIV("dout_uart0", "mout_uart0", EXYNOS5422_DIV_PERIC0,
510 CLK_DIV("dout_uart1", "mout_uart1", EXYNOS5422_DIV_PERIC0,
512 CLK_DIV("dout_uart2", "mout_uart2", EXYNOS5422_DIV_PERIC0,
514 CLK_DIV("dout_uart3", "mout_uart3", EXYNOS5422_DIV_PERIC0,
Indexes created Sat Oct 11 19:10:01 GMT 2025