Lines Matching defs:CLK_MUX
308 #define CLK_MUX(_name, _reg, _bits, _p) \
458 CLK_MUX("mout_sw_aclk200_fsys", EXYNOS5422_SRC_TOP10, __BIT(24),
460 CLK_MUX("mout_sw_aclk200_fsys2", EXYNOS5422_SRC_TOP10, __BIT(12),
462 CLK_MUX("mout_user_aclk200_fsys", EXYNOS5422_SRC_TOP3, __BIT(28),
464 CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12),
466 CLK_MUX("mout_aclk66", EXYNOS5422_SRC_TOP1, __BITS(9,8),
468 CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24),
470 CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12),
473 CLK_MUX("mout_sw_aclk66", EXYNOS5422_SRC_TOP11, __BIT(8),
475 CLK_MUX("mout_user_aclk66_peric", EXYNOS5422_SRC_TOP4, __BIT(8),
478 CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4),
480 CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20),
482 CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8),
484 CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12),
486 CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16),
488 CLK_MUX("mout_uart0", EXYNOS5422_SRC_PERIC0, __BITS(6,4),
490 CLK_MUX("mout_uart1", EXYNOS5422_SRC_PERIC0, __BITS(10,8),
492 CLK_MUX("mout_uart2", EXYNOS5422_SRC_PERIC0, __BITS(14,12),
494 CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16),
Indexes created Sun Oct 12 20:09:57 GMT 2025