Cross Reference: /src/sys/arch/arm/samsung/exynos5422

Lines Matching defs:eclk
698     struct exynos_clk *eclk)
704 	switch (eclk->type) {
722 	clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
726 	    eclk->base.name,
729 	    type, clk_get_rate(&eclk->base));
736 	struct exynos_clk *eclk;
745 	eclk = exynos5422_clock_find_by_id(clock_id);
746 	if (eclk)
747 		return &eclk->base;
754     struct exynos_clk *eclk)
756 	struct exynos_pll_clk *epll = &eclk->u.pll;
759 	KASSERT(eclk->type == EXYNOS_CLK_PLL);
761 	clk_parent = exynos5422_clock_find(eclk->parent);
773     struct exynos_clk *eclk, u_int rate)
781     struct exynos_clk *eclk, struct exynos_clk *eclk_parent)
783 	struct exynos_mux_clk *emux = &eclk->u.mux;
787 	KASSERT(eclk->type == EXYNOS_CLK_MUX);
808     struct exynos_clk *eclk)
810 	struct exynos_mux_clk *emux = &eclk->u.mux;
812 	KASSERT(eclk->type == EXYNOS_CLK_MUX);
824     struct exynos_clk *eclk)
826 	struct exynos_div_clk *ediv = &eclk->u.div;
829 	KASSERT(eclk->type == EXYNOS_CLK_DIV);
831 	clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
842     struct exynos_clk *eclk, u_int rate)
844 	struct exynos_div_clk *ediv = &eclk->u.div;
849 	KASSERT(eclk->type == EXYNOS_CLK_DIV);
851 	clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
874     struct exynos_clk *eclk, bool enable)
876 	struct exynos_gate_clk *egate = &eclk->u.gate;
878 	KASSERT(eclk->type == EXYNOS_CLK_GATE);
898 	struct exynos_clk *eclk;
900 	eclk = exynos5422_clock_find(name);
901 	if (eclk == NULL)
904 	atomic_inc_uint(&eclk->refcnt);
906 	return &eclk->base;
912 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
914 	KASSERT(eclk->refcnt > 0);
916 	atomic_dec_uint(&eclk->refcnt);
922 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
925 	switch (eclk->type) {
927 		return eclk->u.fixed.rate;
929 		return exynos5422_clock_get_rate_pll(priv, eclk);
935 		return exynos5422_clock_get_rate_div(priv, eclk);
937 		panic("exynos5422: unknown eclk type %d", eclk->type);
944 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
948 	switch (eclk->type) {
952 		return exynos5422_clock_set_rate_pll(priv, eclk, rate);
956 		return exynos5422_clock_set_rate_div(priv, eclk, rate);
960 		panic("exynos5422: unknown eclk type %d", eclk->type);
967 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
969 	switch (eclk->type) {
978 		return exynos5422_clock_enable_gate(priv, eclk, true);
980 		panic("exynos5422: unknown eclk type %d", eclk->type);
987 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
989 	switch (eclk->type) {
998 		return exynos5422_clock_enable_gate(priv, eclk, false);
1000 		panic("exynos5422: unknown eclk type %d", eclk->type);
1007 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
1010 	switch (eclk->type) {
1017 		return exynos5422_clock_set_parent_mux(priv, eclk, eclk_parent);
1019 		panic("exynos5422: unknown eclk type %d", eclk->type);
1026 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
1029 	switch (eclk->type) {
1034 		if (eclk->parent != NULL) {
1035 			eclk_parent = exynos5422_clock_find(eclk->parent);
1039 		eclk_parent = exynos5422_clock_get_parent_mux(priv, eclk);
1042 		panic("exynos5422: unknown eclk type %d", eclk->type);
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