Lines Matching defs:dxs
747 struct dmac_xfer_state *dxs;
749 dxs = kmem_alloc(sizeof(*dxs), KM_SLEEP);
751 return ((struct dmac_xfer *)dxs);
757 struct dmac_xfer_state *dxs = (struct dmac_xfer_state *)dx;
763 kmem_free(dxs, sizeof(*dxs));
828 struct dmac_xfer_state *dxs = (struct dmac_xfer_state *)dx;
833 if (dxs->dxs_peripheral != DMAC_PERIPH_NONE &&
834 dxs->dxs_peripheral >= DMAC_N_PERIPH)
837 src = &dxs->dxs_desc[DMAC_DESC_SRC];
838 dst = &dxs->dxs_desc[DMAC_DESC_DST];
840 dxs->dxs_misaligned_flag = false;
842 if ((err = dmac_init_desc(&dxs->dxs_segs[DMAC_DESC_SRC], src, &size,
843 &dxs->dxs_misaligned_flag)))
846 dxs->dxs_loop_notify != DMAC_DONT_LOOP &&
847 (size % dxs->dxs_loop_notify) != 0)
850 if ((err = dmac_init_desc(&dxs->dxs_segs[DMAC_DESC_DST], dst, &size,
851 &dxs->dxs_misaligned_flag)))
854 dxs->dxs_loop_notify != DMAC_DONT_LOOP &&
855 (size % dxs->dxs_loop_notify) != 0)
858 SLIST_INIT(&dxs->dxs_descs);
859 dxs->dxs_channel = DMAC_NO_CHANNEL;
860 dxs->dxs_dcmd = (((uint32_t)dxs->dxs_dev_width) << DCMD_WIDTH_SHIFT) |
861 (((uint32_t)dxs->dxs_burst_size) << DCMD_SIZE_SHIFT);
863 switch (dxs->dxs_flow) {
867 dxs->dxs_dcmd |= DCMD_FLOWSRC;
870 dxs->dxs_dcmd |= DCMD_FLOWTRG;
875 dxs->dxs_dcmd |= DCMD_INCSRCADDR;
877 dxs->dxs_dcmd |= DCMD_INCTRGADDR;
880 if (dxs->dxs_peripheral == DMAC_PERIPH_NONE ||
881 sc->sc_periph[dxs->dxs_peripheral].sp_busy == 0) {
882 dxs->dxs_queue = &sc->sc_queue[DMAC_PRI(dxs->dxs_priority)];
883 SIMPLEQ_INSERT_TAIL(dxs->dxs_queue, dxs, dxs_link);
884 if (dxs->dxs_peripheral != DMAC_PERIPH_NONE)
885 sc->sc_periph[dxs->dxs_peripheral].sp_busy++;
886 dmac_start(sc, DMAC_PRI(dxs->dxs_priority));
888 dxs->dxs_queue = &sc->sc_periph[dxs->dxs_peripheral].sp_queue;
889 SIMPLEQ_INSERT_TAIL(dxs->dxs_queue, dxs, dxs_link);
890 sc->sc_periph[dxs->dxs_peripheral].sp_busy++;
901 struct dmac_xfer_state *ndxs, *dxs = (struct dmac_xfer_state *)dx;
909 queue = dxs->dxs_queue;
911 if (dxs->dxs_channel == DMAC_NO_CHANNEL) {
922 dxs->dxs_queue = NULL;
923 SIMPLEQ_REMOVE(queue, dxs, dmac_xfer_state, dxs_link);
928 dmac_reg_write(sc, DMAC_DCSR(dxs->dxs_channel), 0);
931 rv = dmac_reg_read(sc, DMAC_DCSR(dxs->dxs_channel));
940 dxs->dxs_channel);
945 for (desc = SLIST_FIRST(&dxs->dxs_descs); desc; desc = ndesc) {
951 sc->sc_active[dxs->dxs_channel] = NULL;
952 dmac_free_channel(sc, DMAC_PRI(dxs->dxs_priority),
953 dxs->dxs_channel);
955 if (dxs->dxs_peripheral != DMAC_PERIPH_NONE)
956 dmac_reg_write(sc, DMAC_DRCMR(dxs->dxs_peripheral), 0);
959 dxs->dxs_queue = NULL;
962 if (dxs->dxs_peripheral == DMAC_PERIPH_NONE ||
963 sc->sc_periph[dxs->dxs_peripheral].sp_busy-- == 1 ||
964 queue == &sc->sc_periph[dxs->dxs_peripheral].sp_queue)
972 ndxs = SIMPLEQ_FIRST(&sc->sc_periph[dxs->dxs_peripheral].sp_queue);
973 dxs = ndxs;
974 KDASSERT(dxs != NULL);
975 SIMPLEQ_REMOVE_HEAD(&sc->sc_periph[dxs->dxs_peripheral].sp_queue,
978 dxs->dxs_queue = &sc->sc_queue[DMAC_PRI(dxs->dxs_priority)];
979 SIMPLEQ_INSERT_TAIL(dxs->dxs_queue, dxs, dxs_link);
988 dmac_start(sc, DMAC_PRI(dxs->dxs_priority));
995 struct dmac_xfer_state *dxs;
999 (dxs = SIMPLEQ_FIRST(&sc->sc_queue[priority])) != NULL &&
1014 if (dxs->dxs_misaligned_flag)
1019 dxs->dxs_channel = channel;
1020 sc->sc_active[channel] = dxs;
1021 (void) dmac_continue_xfer(sc, dxs);
1029 dmac_continue_xfer(struct pxadmac_softc *sc, struct dmac_xfer_state *dxs)
1042 src_ds = &dxs->dxs_segs[DMAC_DESC_SRC];
1043 dst_ds = &dxs->dxs_segs[DMAC_DESC_DST];
1044 src_xd = &dxs->dxs_desc[DMAC_DESC_SRC];
1045 dst_xd = &dxs->dxs_desc[DMAC_DESC_DST];
1046 SLIST_INIT(&dxs->dxs_descs);
1056 dxs->dxs_loop_notify != DMAC_DONT_LOOP)
1057 src_size = dxs->dxs_loop_notify;
1064 dxs->dxs_loop_notify != DMAC_DONT_LOOP)
1065 dst_size = dxs->dxs_loop_notify;
1102 dd->dd_dcmd = dxs->dxs_dcmd | this_size;
1111 SLIST_INSERT_HEAD(&dxs->dxs_descs, desc,
1144 if (dxs->dxs_loop_notify != DMAC_DONT_LOOP) {
1152 for (desc = SLIST_FIRST(&dxs->dxs_descs);
1175 if (dxs->dxs_loop_notify == DMAC_DONT_LOOP) {
1179 dd->dd_ddadr = SLIST_FIRST(&dxs->dxs_descs)->d_desc_pa;
1181 if (dxs->dxs_peripheral != DMAC_PERIPH_NONE) {
1182 dmac_reg_write(sc, DMAC_DRCMR(dxs->dxs_peripheral),
1183 dxs->dxs_channel | DRCMR_MAPVLD);
1185 dmac_reg_write(sc, DMAC_DDADR(dxs->dxs_channel),
1186 dxs->dxs_descs)->d_desc_pa);
1187 dmac_reg_write(sc, DMAC_DCSR(dxs->dxs_channel),
1196 struct dmac_xfer_state *dxs;
1206 if ((dxs = sc->sc_active[channel]) == NULL) {
1223 if (dxs->dxs_loop_notify != DMAC_DONT_LOOP &&
1225 (dxs->dxs_done)(&dxs->dxs_xfer, 0);
1236 for (desc = SLIST_FIRST(&dxs->dxs_descs); desc; desc = ndesc) {
1242 if ((dcsr & DCSR_BUSERRINTR) || dmac_continue_xfer(sc, dxs) == 0) {
1252 dmac_free_channel(sc, DMAC_PRI(dxs->dxs_priority), channel);
1253 dxs->dxs_channel = DMAC_NO_CHANNEL;
1254 if (dxs->dxs_peripheral != DMAC_PERIPH_NONE)
1255 dmac_reg_write(sc, DMAC_DRCMR(dxs->dxs_peripheral), 0);
1257 if (dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs == 0 ||
1258 dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs == 0 ||
1264 dxs->dxs_queue = NULL;
1265 rv = 1u << DMAC_PRI(dxs->dxs_priority);
1267 if (dxs->dxs_peripheral != DMAC_PERIPH_NONE &&
1268 --sc->sc_periph[dxs->dxs_peripheral].sp_busy != 0) {
1276 &sc->sc_periph[dxs->dxs_peripheral].sp_queue);
1279 &sc->sc_periph[dxs->dxs_peripheral].sp_queue,
1283 &sc->sc_queue[DMAC_PRI(dxs->dxs_priority)];
1288 (dxs->dxs_done)(&dxs->dxs_xfer,
1299 &sc->sc_queue[DMAC_PRI(dxs->dxs_priority)], dxs,
Indexes created Fri Oct 17 17:09:57 GMT 2025