Cross Reference: /src/sys/arch/arm/xscale/pxa2x0

Lines Matching refs:sc
42 	ohci_softc_t	sc;
53 #define	HREAD4(sc,r)	bus_space_read_4((sc)->sc.iot, (sc)->sc.ioh, (r))
54 #define	HWRITE4(sc,r,v)	bus_space_write_4((sc)->sc.iot, (sc)->sc.ioh, (r), (v))
71 	struct pxaohci_softc *sc = device_private(self);
81 	sc->sc.iot = pxa->pxa_iot;
82 	sc->sc.sc_bus.ub_dmatag = pxa->pxa_dmat;
83 	sc->sc.sc_size = 0;
84 	sc->sc_ih = NULL;
85 	sc->sc.sc_dev = self;
86 	sc->sc.sc_bus.ub_hcpriv = sc;
92 	if (bus_space_map(sc->sc.iot, pxa->pxa_addr, pxa->pxa_size, 0,
93 	    &sc->sc.ioh)) {
94 		aprint_error_dev(sc->sc.sc_dev, "couldn't map memory space\n");
97 	sc->sc.sc_size = pxa->pxa_size;
100 	bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
105 	pxaohci_enable(sc);
108 	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
111 	sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_USBH1, IPL_USB,
112 	    ohci_intr, &sc->sc);
113 	if (sc->sc_ih == NULL) {
114 		aprint_error_dev(sc->sc.sc_dev,
119 	int err = ohci_init(&sc->sc);
121 		aprint_error_dev(sc->sc.sc_dev, "init failed, error=%d\n", err);
129 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
135 	pxa2x0_intr_disestablish(sc->sc_ih);
136 	sc->sc_ih = NULL;
138 	pxaohci_disable(sc);
140 	bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
141 	sc->sc.sc_size = 0;
147 	struct pxaohci_softc *sc = device_private(self);
175 	if (sc->sc_ih) {
176 		pxa2x0_intr_disestablish(sc->sc_ih);
177 		sc->sc_ih = NULL;
184 	ohci_detach(&sc->sc);
193 	pxaohci_disable(sc);
201 	if (sc->sc.sc_size) {
202 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
203 		sc->sc.sc_size = 0;
213 	struct pxaohci_softc *sc = (struct pxaohci_softc *)arg;
217 	sc->sc.sc_bus.ub_usepolling++;
222 		ohci_power(why, &sc->sc);
229 		pxaohci_enable(sc);
231 		ohci_power(why, &sc->sc);
235 	sc->sc.sc_bus.ub_usepolling--;
241 pxaohci_enable(struct pxaohci_softc *sc)
246 	hr = HREAD4(sc, USBHC_HR);
247 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
251 	hr = HREAD4(sc, USBHC_HR);
252 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
255 	hr = HREAD4(sc, USBHC_HR);
256 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
258 	while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR)
262 	hr = HREAD4(sc, USBHC_HR);
263 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
264 	hr = HREAD4(sc, USBHC_HR);
265 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
267 	HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
269 	hr = HREAD4(sc, USBHC_UHCRHDA);
273 pxaohci_disable(struct pxaohci_softc *sc)
278 	hr = HREAD4(sc, USBHC_HR);
279 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
283 	hr = HREAD4(sc, USBHC_HR);
284 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
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