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      1 /*	$NetBSD: pxa2x0_ohci.c,v 1.14 2025/03/31 14:46:42 riastradh Exp $	*/
      2 /*	$OpenBSD: pxa2x0_ohci.c,v 1.19 2005/04/08 02:32:54 dlg Exp $ */
      3 
      4 /*
      5  * Copyright (c) 2005 David Gwynne <dlg (at) openbsd.org>
      6  *
      7  * Permission to use, copy, modify, and distribute this software for any
      8  * purpose with or without fee is hereby granted, provided that the above
      9  * copyright notice and this permission notice appear in all copies.
     10  *
     11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     18  */
     19 
     20 #include <sys/param.h>
     21 #include <sys/systm.h>
     22 #include <sys/device.h>
     23 #include <sys/kernel.h>
     24 
     25 #include <machine/intr.h>
     26 #include <sys/bus.h>
     27 
     28 #include <dev/usb/usb.h>
     29 #include <dev/usb/usbdi.h>
     30 #include <dev/usb/usbdivar.h>
     31 #include <dev/usb/usb_mem.h>
     32 
     33 #include <dev/usb/ohcireg.h>
     34 #include <dev/usb/ohcivar.h>
     35 
     36 #include <arm/xscale/pxa2x0cpu.h>
     37 #include <arm/xscale/pxa2x0reg.h>
     38 #include <arm/xscale/pxa2x0var.h>
     39 #include <arm/xscale/pxa2x0_gpio.h>
     40 
     41 struct pxaohci_softc {
     42 	ohci_softc_t	sc;
     43 
     44 	void		*sc_ih;
     45 };
     46 
     47 #if 0
     48 static void	pxaohci_power(int, void *);
     49 #endif
     50 static void	pxaohci_enable(struct pxaohci_softc *);
     51 static void	pxaohci_disable(struct pxaohci_softc *);
     52 
     53 #define	HREAD4(sc,r)	bus_space_read_4((sc)->sc.iot, (sc)->sc.ioh, (r))
     54 #define	HWRITE4(sc,r,v)	bus_space_write_4((sc)->sc.iot, (sc)->sc.ioh, (r), (v))
     55 
     56 static int
     57 pxaohci_match(device_t parent, struct cfdata *cf, void *aux)
     58 {
     59 	struct pxaip_attach_args *pxa = aux;
     60 
     61 	if (CPU_IS_PXA270 && strcmp(pxa->pxa_name, cf->cf_name) == 0) {
     62 		pxa->pxa_size = PXA2X0_USBHC_SIZE;
     63 		return 1;
     64 	}
     65 	return 0;
     66 }
     67 
     68 static void
     69 pxaohci_attach(device_t parent, device_t self, void *aux)
     70 {
     71 	struct pxaohci_softc *sc = device_private(self);
     72 	struct pxaip_attach_args *pxa = aux;
     73 
     74 #ifdef USB_DEBUG
     75 	{
     76 		//extern int ohcidebug;
     77 		//ohcidebug = 16;
     78 	}
     79 #endif
     80 
     81 	sc->sc.iot = pxa->pxa_iot;
     82 	sc->sc.sc_bus.ub_dmatag = pxa->pxa_dmat;
     83 	sc->sc.sc_size = 0;
     84 	sc->sc_ih = NULL;
     85 	sc->sc.sc_dev = self;
     86 	sc->sc.sc_bus.ub_hcpriv = sc;
     87 
     88 	aprint_normal("\n");
     89 	aprint_naive("\n");
     90 
     91 	/* Map I/O space */
     92 	if (bus_space_map(sc->sc.iot, pxa->pxa_addr, pxa->pxa_size, 0,
     93 	    &sc->sc.ioh)) {
     94 		aprint_error_dev(sc->sc.sc_dev, "couldn't map memory space\n");
     95 		return;
     96 	}
     97 	sc->sc.sc_size = pxa->pxa_size;
     98 
     99 	/* XXX copied from ohci_pci.c. needed? */
    100 	bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size,
    101 	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
    102 
    103 	/* start the usb clock */
    104 	pxa2x0_clkman_config(CKEN_USBHC, 1);
    105 	pxaohci_enable(sc);
    106 
    107 	/* Disable interrupts, so we don't get any spurious ones. */
    108 	bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE,
    109 	    OHCI_MIE);
    110 
    111 	sc->sc_ih = pxa2x0_intr_establish(PXA2X0_INT_USBH1, IPL_USB,
    112 	    ohci_intr, &sc->sc);
    113 	if (sc->sc_ih == NULL) {
    114 		aprint_error_dev(sc->sc.sc_dev,
    115 		    "unable to establish interrupt\n");
    116 		goto free_map;
    117 	}
    118 
    119 	int err = ohci_init(&sc->sc);
    120 	if (err) {
    121 		aprint_error_dev(sc->sc.sc_dev, "init failed, error=%d\n", err);
    122 		goto free_intr;
    123 	}
    124 
    125 #if 0
    126 	pmf_device_register1(self, ohci_suspend, ohci_resume, ohci_shutdown);
    127 #endif
    128 
    129 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
    130 	    CFARGS_NONE);
    131 
    132 	return;
    133 
    134 free_intr:
    135 	pxa2x0_intr_disestablish(sc->sc_ih);
    136 	sc->sc_ih = NULL;
    137 free_map:
    138 	pxaohci_disable(sc);
    139 	pxa2x0_clkman_config(CKEN_USBHC, 0);
    140 	bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
    141 	sc->sc.sc_size = 0;
    142 }
    143 
    144 static int
    145 pxaohci_detach(device_t self, int flags)
    146 {
    147 	struct pxaohci_softc *sc = device_private(self);
    148 	int error;
    149 
    150 	/*
    151 	 * Detach the USB child first.  Disconnects all USB devices and
    152 	 * prevents connecting new ones.
    153 	 */
    154 	error = config_detach_children(self, flags);
    155 	if (error)
    156 		return error;
    157 
    158 	/*
    159 	 * Shut down the controller and block interrupts at the device
    160 	 * level.  Once we have shut down the controller, the shutdown
    161 	 * handler no longer needed -- deregister it from PMF.
    162 	 * (Harmless to call ohci_shutdown more than once, so no
    163 	 * synchronization needed.)
    164 	 */
    165 	ohci_shutdown(self, 0);
    166 #if 0
    167 	pmf_device_deregister(self);
    168 #endif
    169 
    170 	/*
    171 	 * Interrupts are blocked at the device level by ohci_shutdown.
    172 	 * Disestablish the interrupt handler.  This waits for it to
    173 	 * complete on all CPUs.
    174 	 */
    175 	if (sc->sc_ih) {
    176 		pxa2x0_intr_disestablish(sc->sc_ih);
    177 		sc->sc_ih = NULL;
    178 	}
    179 
    180 	/*
    181 	 * Free the bus-independent ohci(4) state now that the
    182 	 * interrupt handler has ceased to run on all CPUs.
    183 	 */
    184 	ohci_detach(&sc->sc);
    185 
    186 	/*
    187 	 * Issue a Full Host Reset to disable the host controller
    188 	 * interface.
    189 	 *
    190 	 * XXX Is this necessary or is it redundant with ohci_shutdown?
    191 	 * Should it be done in ohci_shutdown as well?
    192 	 */
    193 	pxaohci_disable(sc);
    194 
    195 	/* stop clock */
    196 	pxa2x0_clkman_config(CKEN_USBHC, 0);
    197 
    198 	/*
    199 	 * Unmap the registers now that we're all done with them.
    200 	 */
    201 	if (sc->sc.sc_size) {
    202 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
    203 		sc->sc.sc_size = 0;
    204 	}
    205 
    206 	return 0;
    207 }
    208 
    209 #if 0
    210 static void
    211 pxaohci_power(int why, void *arg)
    212 {
    213 	struct pxaohci_softc *sc = (struct pxaohci_softc *)arg;
    214 	int s;
    215 
    216 	s = splhardusb();
    217 	sc->sc.sc_bus.ub_usepolling++;
    218 	switch (why) {
    219 	case PWR_STANDBY:
    220 	case PWR_SUSPEND:
    221 #if 0
    222 		ohci_power(why, &sc->sc);
    223 #endif
    224 		pxa2x0_clkman_config(CKEN_USBHC, 0);
    225 		break;
    226 
    227 	case PWR_RESUME:
    228 		pxa2x0_clkman_config(CKEN_USBHC, 1);
    229 		pxaohci_enable(sc);
    230 #if 0
    231 		ohci_power(why, &sc->sc);
    232 #endif
    233 		break;
    234 	}
    235 	sc->sc.sc_bus.ub_usepolling--;
    236 	splx(s);
    237 }
    238 #endif
    239 
    240 static void
    241 pxaohci_enable(struct pxaohci_softc *sc)
    242 {
    243 	uint32_t hr;
    244 
    245 	/* Full host reset */
    246 	hr = HREAD4(sc, USBHC_HR);
    247 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
    248 
    249 	DELAY(USBHC_RST_WAIT);
    250 
    251 	hr = HREAD4(sc, USBHC_HR);
    252 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
    253 
    254 	/* Force system bus interface reset */
    255 	hr = HREAD4(sc, USBHC_HR);
    256 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FSBIR);
    257 
    258 	while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR)
    259 		DELAY(3);
    260 
    261 	/* Enable the ports (physically only one, only enable that one?) */
    262 	hr = HREAD4(sc, USBHC_HR);
    263 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_SSE));
    264 	hr = HREAD4(sc, USBHC_HR);
    265 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) &
    266 			~(USBHC_HR_SSEP1 | USBHC_HR_SSEP2 | USBHC_HR_SSEP3));
    267 	HWRITE4(sc, USBHC_HIE, USBHC_HIE_RWIE | USBHC_HIE_UPRIE);
    268 
    269 	hr = HREAD4(sc, USBHC_UHCRHDA);
    270 }
    271 
    272 static void
    273 pxaohci_disable(struct pxaohci_softc *sc)
    274 {
    275 	uint32_t hr;
    276 
    277 	/* Full host reset */
    278 	hr = HREAD4(sc, USBHC_HR);
    279 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) | USBHC_HR_FHR);
    280 
    281 	DELAY(USBHC_RST_WAIT);
    282 
    283 	hr = HREAD4(sc, USBHC_HR);
    284 	HWRITE4(sc, USBHC_HR, (hr & USBHC_HR_MASK) & ~(USBHC_HR_FHR));
    285 }
    286 
    287 
    288 CFATTACH_DECL2_NEW(pxaohci, sizeof(struct pxaohci_softc),
    289     pxaohci_match, pxaohci_attach, pxaohci_detach, ohci_activate, NULL,
    290     ohci_childdet);
    291