Lines Matching defs:insn
70 #define DUMP_INSN(insn) \
71 printf("%s: insn={adv=%d,siz=%d,op=%04x,w1=%04x}\n", \
73 (insn)->is_advance, (insn)->is_datasize, \
74 (insn)->is_opcode, (insn)->is_word1)
77 #define DUMP_INSN(insn) do {} while (/* CONSTCOND */ 0)
89 static struct instruction insn;
94 /* initialize insn.is_datasize to tell it is *not* initialized */
95 insn.is_datasize = -1;
106 insn.is_pc = frame->f_pc;
107 insn.is_nextpc = 0;
122 insn.is_nextpc = frame->f_pc;
124 insn.is_pc = frame->f_fmt4.f_fslw;
125 frame->f_pc = insn.is_pc;
128 if (ufetch_short((void *)(insn.is_pc), &sval)) {
134 DPRINTF(("%s: not coproc. insn.: opcode=0x%x\n",
144 insn.is_opcode = sval;
147 if (ufetch_short((void *)(insn.is_pc + 2), &sval)) {
151 insn.is_word1 = sval;
153 insn.is_advance = 4;
155 DUMP_INSN(&insn);
167 sig = fpu_emul_fmovm(&fe, &insn);
170 sig = fpu_emul_fmovmcr(&fe, &insn);
176 sig = fpu_emul_fstore(&fe, &insn);
180 sig = fpu_emul_fmovecr(&fe, &insn);
184 sig = fpu_emul_fscale(&fe, &insn);
188 sig = fpu_emul_arith(&fe, &insn);
199 sig = fpu_emul_brcc(&fe, &insn);
203 sig = fpu_emul_type1(&fe, &insn);
214 insn.is_opcode));
218 DUMP_INSN(&insn);
226 frame->f_pc += insn.is_advance;
230 sig, insn.is_opcode, insn.is_word1);
237 if (insn.is_nextpc)
238 frame->f_pc = insn.is_nextpc;
260 * update fpsr accrued exception bits; each insn doesn't have to
333 fpu_emul_fmovmcr(struct fpemu *fe, struct instruction *insn)
345 reglist = (insn->is_word1 & 0x1c00) >> 10;
347 fpu_to_mem = insn->is_word1 & 0x2000;
350 modreg = insn->is_opcode & 077;
377 insn->is_datasize = regcount * 4;
378 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg);
386 if ((insn->is_ea.ea_flags & EA_DIRECT)) {
387 if (insn->is_ea.ea_regnum < 8) {
411 sig = fpu_store_ea(frame, insn, &insn->is_ea, (char *)tmp);
415 sig = fpu_load_ea(frame, insn, &insn->is_ea, (char *)tmp);
445 fpu_emul_fmovm(struct fpemu *fe, struct instruction *insn)
456 insn->is_datasize = 12;
457 word1 = insn->is_word1;
479 modreg = insn->is_opcode & 077;
493 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg);
500 if (insn->is_ea.ea_flags & EA_PREDECR) {
512 sig = fpu_store_ea(frame, insn, &insn->is_ea,
520 sig = fpu_load_ea(frame, insn, &insn->is_ea,
598 fpu_emul_arith(struct fpemu *fe, struct instruction *insn)
615 DUMP_INSN(insn);
620 word1 = insn->is_word1;
631 DUMP_INSN(insn);
644 insn->is_datasize = 8;
646 insn->is_datasize = 4;
648 insn->is_datasize = 2;
650 insn->is_datasize = 1;
652 insn->is_datasize = 12;
660 modreg = insn->is_opcode & 077;
666 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg);
672 if (insn->is_ea.ea_flags == EA_DIRECT &&
673 insn->is_datasize > 4) {
679 DUMP_INSN(insn);
683 flags = insn->is_ea.ea_flags;
684 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd';
687 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7);
690 printf("pc@(%d)\n", insn->is_ea.ea_offset);
695 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7);
697 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7);
700 insn->is_ea.ea_regnum & 7,
701 insn->is_ea.ea_offset);
704 insn->is_ea.ea_regnum & 7);
706 printf("0x%08x\n", insn->is_ea.ea_absaddr);
709 insn->is_ea.ea_immed[0],
710 insn->is_ea.ea_immed[1],
711 insn->is_ea.ea_immed[2]);
713 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7);
717 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf);
732 buf[0], buf[1], buf[2], insn->is_datasize));
736 DUMP_INSN(insn);
911 insn->is_opcode, insn->is_word1));
950 DUMP_INSN(insn);
1059 fpu_emul_type1(struct fpemu *fe, struct instruction *insn)
1065 branch = test_cc(fe, insn->is_word1);
1071 switch (insn->is_opcode & 070) {
1075 insn->is_advance = 6;
1078 uint16_t count = frame->f_regs[insn->is_opcode & 7];
1081 if (ufetch_short((void *)(insn->is_pc +
1082 insn->is_advance),
1094 insn->is_advance += displ;
1096 insn->is_nextpc = insn->is_pc +
1097 insn->is_advance;
1100 insn->is_advance = 6;
1103 frame->f_regs[insn->is_opcode & 7] &= 0xffff0000;
1104 frame->f_regs[insn->is_opcode & 7] |= (uint32_t)count;
1110 if ((insn->is_opcode & 07) >= 2) {
1111 switch (insn->is_opcode & 07) {
1122 insn->is_advance = advance;
1133 insn->is_datasize = 1; /* always byte */
1134 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode);
1139 sig = fpu_store_ea(frame, insn, &insn->is_ea, (char *)&branch);
1151 fpu_emul_brcc(struct fpemu *fe, struct instruction *insn)
1160 displ = insn->is_word1;
1162 if (insn->is_opcode & 0x40) {
1163 if (ufetch_short((void *)(insn->is_pc + insn->is_advance),
1171 insn->is_advance += 2;
1178 /* XXX: If CC, insn->is_pc += displ */
1179 sig = test_cc(fe, insn->is_opcode);
1189 insn->is_advance = displ + 2;
1191 insn->is_nextpc = insn->is_pc + insn->is_advance;
1195 DPRINTF(("%s: %s insn @ %x (%x+%x) (disp=%x)\n", __func__,
1197 insn->is_pc + insn->is_advance, insn->is_pc, insn->is_advance,
Indexes created Tue Oct 14 06:10:07 GMT 2025