Lines Matching refs:psc_reg2
193 psc_reg2(PSC_ENETRD_CTL) = 0x8800;
194 psc_reg2(PSC_ENETRD_CTL) = 0x1000;
195 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x1100;
196 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x1100;
199 psc_reg2(PSC_ENETWR_CTL) = 0x8800;
200 psc_reg2(PSC_ENETWR_CTL) = 0x1000;
201 psc_reg2(PSC_ENETWR_CMD + PSC_SET0) = 0x1100;
202 psc_reg2(PSC_ENETWR_CMD + PSC_SET1) = 0x1100;
212 psc_reg2(PSC_ENETWR_CTL) = 0x9000;
213 psc_reg2(PSC_ENETRD_CTL) = 0x9000;
214 psc_reg2(PSC_ENETWR_CTL) = 0x0400;
215 psc_reg2(PSC_ENETRD_CTL) = 0x0400;
251 psc_reg2(PSC_ENETWR_CMD + sc->sc_txset) = 0x9800;
279 status = psc_reg2(PSC_ENETRD_CTL);
292 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x1100;
304 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9000;
338 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9800;
342 status = psc_reg2(PSC_ENETWR_CTL);
352 psc_reg2(PSC_ENETWR_CMD + sc->sc_txseti) = 0x100;
368 psc_reg2(PSC_ENETRD_CTL) = 0x8800;
370 psc_reg2(PSC_ENETRD_CTL) = 0x400;
372 psc_reg2(PSC_ENETRD_CTL) = 0x8800;
374 psc_reg2(PSC_ENETRD_CTL) = 0x400;
380 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x9800;
381 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x9800;
388 psc_reg2(PSC_ENETRD_CMD + set) = 0x0100;
391 psc_reg2(PSC_ENETRD_CMD + set) = 0x9800;
400 psc_reg2(PSC_ENETWR_CTL) = 0x8800;
404 psc_reg2(PSC_ENETWR_CTL) = 0x400;
Indexes created Sun Oct 26 21:10:03 GMT 2025