Lines Matching refs:REG_WRITE
165 #define REG_WRITE(o, v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
224 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));
225 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));
226 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));
227 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));
242 REG_WRITE(VLAN_G1_REG, i);
244 REG_WRITE(VLAN_G2_REG, i);
253 REG_WRITE(PORT_CONF0_REG,
255 REG_WRITE(CPUP_CONF_REG,
266 REG_WRITE(PHY_CNTL2_REG,
270 REG_WRITE(ADMSW_SW_RES, 0x1);
274 REG_WRITE(ADMSW_BOOT_DONE, ADMSW_BOOT_DONE_BO);
277 REG_WRITE(CPUP_CONF_REG,
281 REG_WRITE(PORT_CONF0_REG, PORT_CONF0_EMCP_MASK | PORT_CONF0_EMBP_MASK);
283 REG_WRITE(PHY_CNTL2_REG,
287 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);
289 REG_WRITE(ADMSW_INT_MASK, INT_MASK);
290 REG_WRITE(ADMSW_INT_ST, INT_MASK);
301 REG_WRITE(FC_TH_REG,
307 REG_WRITE(MAC_WT1_REG,
312 REG_WRITE(MAC_WT0_REG, (i<<MAC_WT0_VLANID_SHIFT) |
320 REG_WRITE(ADM5120_WDOG1, wdog1 & ~ADM5120_WDOG1_WDE);
660 REG_WRITE(SEND_TRIG_REG, 1);
804 REG_WRITE(ADMSW_INT_ST, pending);
1033 REG_WRITE(CPUP_CONF_REG,
1037 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1040 REG_WRITE(ADMSW_INT_MASK, REG_READ(ADMSW_INT_MASK) &
1076 REG_WRITE(CPUP_CONF_REG,
1082 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1085 REG_WRITE(ADMSW_INT_MASK, INT_MASK);
1136 REG_WRITE(MAC_WT1_REG,
1141 REG_WRITE(MAC_WT0_REG,
1168 REG_WRITE(CPUP_CONF_REG, conf);
1255 REG_WRITE(PHY_CNTL2_REG, new);
Indexes created Mon Oct 20 05:10:11 GMT 2025