Lines Matching defs:REGVAL
88 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
170 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff;
171 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff;
172 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff;
173 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff;
174 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff;
175 REGVAL(ic0_base + IC_TEST_BIT) = 0;
177 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff;
178 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff;
179 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff;
180 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff;
181 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff;
182 REGVAL(ic1_base + IC_TEST_BIT) = 0;
236 REGVAL(icu_base + IC_CONFIG2_SET) = irq;
237 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
238 REGVAL(icu_base + IC_CONFIG0_SET) = irq;
241 REGVAL(icu_base + IC_CONFIG2_SET) = irq;
242 REGVAL(icu_base + IC_CONFIG1_SET) = irq;
243 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
250 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq;
252 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq;
255 REGVAL(icu_base + IC_SOURCE_SET) = irq;
258 REGVAL(icu_base + IC_MASK_SET) = irq;
261 REGVAL(icu_base + IC_WAKEUP_SET) = irq;
296 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq;
297 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq;
298 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq;
301 REGVAL(icu_base + IC_MASK_CLEAR) = irq;
302 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq;
330 * irqstat = REGVAL(
340 irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
344 irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
348 irqstat = REGVAL(icu_base + IC_REQUEST0_INT);
352 irqstat = REGVAL(icu_base + IC_REQUEST1_INT);
355 irqmask = REGVAL(icu_base + IC_MASK_READ);
364 if (REGVAL(icu_base + IC_MASK_READ) & mask) {
365 REGVAL(icu_base + IC_MASK_CLEAR) = mask;
366 REGVAL(icu_base + IC_MASK_SET) = mask;
396 REGVAL(icu_base + IC_MASK_SET) = mask;
397 REGVAL(icu_base + IC_WAKEUP_SET) = mask;
417 REGVAL(icu_base + IC_MASK_CLEAR) = mask;
418 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask;