Cross Reference: /src/sys/arch/mips/cavium/dev/octeon

Lines Matching refs:SET
389 			SET(prt_cfg, PRTN_CFG_EN);
439 		SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_BP));
441 		SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_IGN_FULL));
443 		SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_EN));
446 		SET(ovr_bp, __SHIFTIN(__BIT(index), TX_OVR_BP_IGN_FULL));
469 	SET(tx_int_xxx,
484 	SET(rx_int_xxx, 0 |
535 		SET(tmp, rx_frm_ctl);
585 		SET(ctl, RXN_ADR_CTL_BCST);
592 		SET(ctl, RXN_ADR_CTL_CAM_MODE);
616 			SET(ifp->if_flags, IFF_ALLMULTI);
624 			SET(ifp->if_flags, IFF_ALLMULTI);
631 		SET(cam_en, __BIT(multi));
640 			SET(tmp, (uint64_t)enm->enm_addrlo[i] << (8 * multi));
847 		 * 10/100Mbps: set SLOT to 0x40
852 		 * 10/100Mbps: set BURST to 0x0
878 		 *  10/100Mbps: set SLOT to 0x40
883 		 *  10/100Mbps: set BURST to 0x0
909 		 * > 1000Mbps: set SLOT to 0x200
914 		 * > 1000Mbps: set BURST to 0x2000
922 		SET(prt_cfg, PRTN_CFG_SLOTTIME);
928 		SET(prt_cfg, PRTN_CFG_SPEED);
937 		SET(prt_cfg, PRTN_CFG_SLOTTIME);
938 		SET(prt_cfg, PRTN_CFG_SPEED);
949 		SET(prt_cfg, PRTN_CFG_DUPLEX);
972 	 * never be set to less than 0x4. This register cannot exceed
1019 	/* Set link timer interval to 1.6ms.  Timer multiple is 1024 (2^10). */
1021 	 * XXX Should set timer to 10ms if not in SGMII mode (ie,
1026 	SET(timer_count,
1032 	SET(ctl_reg, PCS_MR_CONTROL_RESET);
1050 	SET(ctl_reg, PCS_MR_CONTROL_AN_EN);
1051 	SET(ctl_reg, PCS_MR_CONTROL_RST_AN);
1084 		SET(prt_cfg, PRTN_CFG_DUPLEX);
1095 		SET(misc_ctl, PCS_MISC_CTL_GMXENO);
1102 		SET(prt_cfg, PRTN_CFG_SPEED_MSB);
1118 		SET(prt_cfg, PRTN_CFG_SPEED);
1120 		SET(prt_cfg, PRTN_CFG_SLOTTIME);
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