Lines Matching refs:UINT64_C
126 #define RXN_INT_REG_XXX_63_19 UINT64_C(0xfffffffffff80000)
127 #define RXN_INT_REG_PHY_DUPX UINT64_C(0x0000000000040000)
128 #define RXN_INT_REG_PHY_SPD UINT64_C(0x0000000000020000)
129 #define RXN_INT_REG_PHY_LINK UINT64_C(0x0000000000010000)
130 #define RXN_INT_REG_IFGERR UINT64_C(0x0000000000008000)
131 #define RXN_INT_REG_COLDET UINT64_C(0x0000000000004000)
132 #define RXN_INT_REG_FALERR UINT64_C(0x0000000000002000)
133 #define RXN_INT_REG_RSVERR UINT64_C(0x0000000000001000)
134 #define RXN_INT_REG_PCTERR UINT64_C(0x0000000000000800)
135 #define RXN_INT_REG_OVRERR UINT64_C(0x0000000000000400)
136 #define RXN_INT_REG_NIBERR UINT64_C(0x0000000000000200)
137 #define RXN_INT_REG_SKPERR UINT64_C(0x0000000000000100)
138 #define RXN_INT_REG_RCVERR UINT64_C(0x0000000000000080)
139 #define RXN_INT_REG_LENERR UINT64_C(0x0000000000000040)
140 #define RXN_INT_REG_ALNERR UINT64_C(0x0000000000000020)
141 #define RXN_INT_REG_FCSERR UINT64_C(0x0000000000000010)
142 #define RXN_INT_REG_JABBER UINT64_C(0x0000000000000008)
143 #define RXN_INT_REG_MAXERR UINT64_C(0x0000000000000004)
144 #define RXN_INT_REG_CAREXT UINT64_C(0x0000000000000002)
145 #define RXN_INT_REG_MINERR UINT64_C(0x0000000000000001)
149 #define RXN_INT_EN_XXX_63_19 UINT64_C(0xfffffffffff80000)
150 #define RXN_INT_EN_PHY_DUPX UINT64_C(0x0000000000040000)
151 #define RXN_INT_EN_PHY_SPD UINT64_C(0x0000000000020000)
152 #define RXN_INT_EN_PHY_LINK UINT64_C(0x0000000000010000)
153 #define RXN_INT_EN_IFGERR UINT64_C(0x0000000000008000)
154 #define RXN_INT_EN_COLDET UINT64_C(0x0000000000004000)
155 #define RXN_INT_EN_FALERR UINT64_C(0x0000000000002000)
156 #define RXN_INT_EN_RSVERR UINT64_C(0x0000000000001000)
157 #define RXN_INT_EN_PCTERR UINT64_C(0x0000000000000800)
158 #define RXN_INT_EN_OVRERR UINT64_C(0x0000000000000400)
159 #define RXN_INT_EN_NIBERR UINT64_C(0x0000000000000200)
160 #define RXN_INT_EN_SKPERR UINT64_C(0x0000000000000100)
161 #define RXN_INT_EN_RCVERR UINT64_C(0x0000000000000080)
162 #define RXN_INT_EN_LENERR UINT64_C(0x0000000000000040)
163 #define RXN_INT_EN_ALNERR UINT64_C(0x0000000000000020)
164 #define RXN_INT_EN_FCSERR UINT64_C(0x0000000000000010)
165 #define RXN_INT_EN_JABBER UINT64_C(0x0000000000000008)
166 #define RXN_INT_EN_MAXERR UINT64_C(0x0000000000000004)
167 #define RXN_INT_EN_CAREXT UINT64_C(0x0000000000000002)
168 #define RXN_INT_EN_MINERR UINT64_C(0x0000000000000001)
172 #define PRTN_CFG_XXX_63_9 UINT64_C(0xfffffffffffffe00)
173 #define PRTN_CFG_SPEED_MSB UINT64_C(0x0000000000000100)
174 #define PRTN_CFG_XXX_7_4 UINT64_C(0x00000000000000f0)
175 #define PRTN_CFG_SLOTTIME UINT64_C(0x0000000000000008)
176 #define PRTN_CFG_DUPLEX UINT64_C(0x0000000000000004)
177 #define PRTN_CFG_SPEED UINT64_C(0x0000000000000002)
178 #define PRTN_CFG_EN UINT64_C(0x0000000000000001)
182 #define RXN_FRM_CTL_XXX_63_11 UINT64_C(0xfffffffffffff800)
183 #define RXN_FRM_CTL_NULL_DIS UINT64_C(0x0000000000000400)
184 #define RXN_FRM_CTL_PRE_ALIGN UINT64_C(0x0000000000000200)
185 #define RXN_FRM_CTL_PAD_LEN UINT64_C(0x0000000000000100)
186 #define RXN_FRM_CTL_VLAN_LEN UINT64_C(0x0000000000000080)
187 #define RXN_FRM_CTL_PRE_FREE UINT64_C(0x0000000000000040)
188 #define RXN_FRM_CTL_CTL_SMAC UINT64_C(0x0000000000000020)
189 #define RXN_FRM_CTL_CTL_MCST UINT64_C(0x0000000000000010)
190 #define RXN_FRM_CTL_CTL_BCK UINT64_C(0x0000000000000008)
191 #define RXN_FRM_CTL_CTL_DRP UINT64_C(0x0000000000000004)
192 #define RXN_FRM_CTL_PRE_STRP UINT64_C(0x0000000000000002)
193 #define RXN_FRM_CTL_PRE_CHK UINT64_C(0x0000000000000001)
197 #define RXN_FRM_CKK_XXX_63_10 UINT64_C(0xfffffffffffffc00)
198 #define RXN_FRM_CHK_NIBERR UINT64_C(0x0000000000000200)
199 #define RXN_FRM_CHK_SKPERR UINT64_C(0x0000000000000100)
200 #define RXN_FRM_CHK_RCVERR UINT64_C(0x0000000000000080)
201 #define RXN_FRM_CHK_LENERR UINT64_C(0x0000000000000040)
202 #define RXN_FRM_CHK_ALNERR UINT64_C(0x0000000000000020)
203 #define RXN_FRM_CHK_FCSERR UINT64_C(0x0000000000000010)
204 #define RXN_FRM_CHK_JABBER UINT64_C(0x0000000000000008)
205 #define RXN_FRM_CHK_MAXERR UINT64_C(0x0000000000000004)
206 #define RXN_FRM_CHK_CAREXT UINT64_C(0x0000000000000002)
207 #define RXN_FRM_CHK_MINERR UINT64_C(0x0000000000000001)
211 #define RXN_RRM_MIN_XXX_63_16 UINT64_C(0xffffffffffff0000)
212 #define RXN_RRM_MIN_LEN UINT64_C(0x000000000000ffff)
216 #define RXN_RRM_MAX_XXX_63_16 UINT64_C(0xffffffffffff0000)
217 #define RXN_RRM_MAX_LEN UINT64_C(0x000000000000ffff)
221 #define RXN_JABBER_XXX_63_16 UINT64_C(0xffffffffffff0000)
222 #define RXN_JABBER_CNT UINT64_C(0x000000000000ffff)
226 #define RXN_DECISION_XXX_63_5 UINT64_C(0xffffffffffffffe0)
227 #define RXN_DECISION_CNT UINT64_C(0x000000000000001f)
231 #define RXN_UDD_SKP_XXX_63_9 UINT64_C(0xfffffffffffffe00)
232 #define RXN_UDD_SKP_FCSSEL UINT64_C(0x0000000000000100)
233 #define RXN_UDD_SKP_XXX_7 UINT64_C(0x0000000000000080)
234 #define RXN_UDD_SKP_LEN UINT64_C(0x000000000000007f)
238 #define RXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe)
239 #define RXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001)
243 #define RXN_IFG_XXX_63_4 UINT64_C(0xfffffffffffffff0)
244 #define RXN_IFG_IFG UINT64_C(0x000000000000000f)
248 #define RXN_RX_INBND_XXX_63_4 UINT64_C(0xfffffffffffffff0)
249 #define RXN_RX_INBND_DUPLEX UINT64_C(0x0000000000000008)
252 #define RXN_RX_INBND_SPEED UINT64_C(0x0000000000000006)
257 #define RXN_RX_INBND_STATUS UINT64_C(0x0000000000000001)
261 #define RXN_STATS_PKTS_XXX_63_32 UINT64_C(0xffffffff00000000)
262 #define RXN_STATS_PKTS_CNT UINT64_C(0x00000000ffffffff)
266 #define RXN_STATS_OCTS_XXX_63_48 UINT64_C(0xffff000000000000)
267 #define RXN_STATS_OCTS_CNT UINT64_C(0x0000ffffffffffff)
271 #define RXN_STATS_PKTS_CTL_XXX_63_32 UINT64_C(0xffffffff00000000)
272 #define RXN_STATS_PKTS_CTL_CNT UINT64_C(0x00000000ffffffff)
276 #define RXN_STATS_OCTS_CTL_XXX_63_48 UINT64_C(0xffff000000000000)
277 #define RXN_STATS_OCTS_CTL_CNT UINT64_C(0x0000ffffffffffff)
281 #define RXN_STATS_PKTS_DMAC_XXX_63_32 UINT64_C(0xffffffff00000000)
282 #define RXN_STATS_PKTS_DMAC_CNT UINT64_C(0x00000000ffffffff)
286 #define RXN_STATS_OCTS_DMAC_XXX_63_48 UINT64_C(0xffff000000000000)
287 #define RXN_STATS_OCTS_DMAC_CNT UINT64_C(0x0000ffffffffffff)
291 #define RXN_STATS_PKTS_DRP_XXX_63_48 UINT64_C(0xffffffff00000000)
292 #define RXN_STATS_PKTS_DRP_CNT UINT64_C(0x00000000ffffffff)
296 #define RXN_STATS_OCTS_DRP_XXX_63_48 UINT64_C(0xffff000000000000)
297 #define RXN_STATS_OCTS_DRP_CNT UINT64_C(0x0000ffffffffffff)
301 #define RXN_STATS_PKTS_BAD_XXX_63_48 UINT64_C(0xffffffff00000000)
302 #define RXN_STATS_PKTS_BAD_CNT UINT64_C(0x00000000ffffffff)
306 #define RXN_ADR_CTL_XXX_63_4 UINT64_C(0xfffffffffffffff0)
307 #define RXN_ADR_CTL_CAM_MODE UINT64_C(0x0000000000000008)
310 #define RXN_ADR_CTL_MCST UINT64_C(0x0000000000000006)
315 #define RXN_ADR_CTL_BCST UINT64_C(0x0000000000000001)
319 #define RXN_ADR_CAM_EN_XXX_63_8 UINT64_C(0xffffffffffffff00)
320 #define RXN_ADR_CAM_EN_EN UINT64_C(0x00000000000000ff)
323 #define RXN_ADR_CAMN_ADR UINT64_C(0xffffffffffffffff)
327 #define TXN_CLK_XXX_63_6 UINT64_C(0xffffffffffffffc0)
328 #define TXN_CLK_CLK_CNT UINT64_C(0x000000000000003f)
332 #define TXN_THRESH_XXX_63_6 UINT64_C(0xffffffffffffffc0)
333 #define TXN_THRESH_CNT UINT64_C(0x000000000000003f)
337 #define TXN_APPEND_XXX_63_4 UINT64_C(0xfffffffffffffff0)
338 #define TXN_APPEND_FORCE_FCS UINT64_C(0x0000000000000008)
339 #define TXN_APPEND_FCS UINT64_C(0x0000000000000004)
340 #define TXN_APPEND_PAD UINT64_C(0x0000000000000002)
341 #define TXN_APPEND_PREAMBLE UINT64_C(0x0000000000000001)
345 #define TXN_SLOT_XXX_63_10 UINT64_C(0xfffffffffffffc00)
346 #define TXN_SLOT_SLOT UINT64_C(0x00000000000003ff)
350 #define TXN_BURST_XXX_63_16 UINT64_C(0xffffffffffff0000)
351 #define TXN_BURST_BURST UINT64_C(0x000000000000ffff)
355 #define SMACN_XXX_63_48 UINT64_C(0xffff000000000000)
356 #define SMACN_SMAC UINT64_C(0x0000ffffffffffff)
360 #define TXN_PAUSE_PKT_TIME_XXX_63_16 UINT64_C(0xffffffffffff0000)
361 #define TXN_PAUSE_PKT_TIME_TIME UINT64_C(0x000000000000ffff)
365 #define TXN_MIN_PKT_XXX_63_8 UINT64_C(0xffffffffffffff00)
366 #define TXN_MIN_PKT_MIN_SIZE UINT64_C(0x00000000000000ff)
370 #define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 UINT64_C(0xffffffffffff0000)
371 #define TXN_PAUSE_PKT_INTERVAL_INTERVAL UINT64_C(0x000000000000ffff)
375 #define TXN_SOFT_PAUSE_XXX_63_16 UINT64_C(0xffffffffffff0000)
376 #define TXN_SOFT_PAUSE_TIME UINT64_C(0x000000000000ffff)
380 #define TXN_PAUSE_TOGO_XXX_63_16 UINT64_C(0xffffffffffff0000)
381 #define TXN_PAUSE_TOGO_TIME UINT64_C(0x000000000000ffff)
385 #define TXN_PAUSE_ZERO_XXX_63_1 UINT64_C(0xfffffffffffffffe)
386 #define TXN_PAUSE_ZERO_SEND UINT64_C(0x0000000000000001)
390 #define TXN_STATS_CTL_XXX_63_1 UINT64_C(0xfffffffffffffffe)
391 #define TXN_STATS_CTL_RD_CLR UINT64_C(0x0000000000000001)
395 #define TXN_CTL_XXX_63_2 UINT64_C(0xfffffffffffffffc)
396 #define TXN_CTL_XSDEF_EN UINT64_C(0x0000000000000002)
397 #define TXN_CTL_XSCOL_EN UINT64_C(0x0000000000000001)
401 #define TXN_STAT0_XSDEF UINT64_C(0xffffffff00000000)
402 #define TXN_STAT0_XSCOL UINT64_C(0x00000000ffffffff)
406 #define TXN_STAT1_SCOL UINT64_C(0xffffffff00000000)
407 #define TXN_STAT1_MSCOL UINT64_C(0x00000000ffffffff)
411 #define TXN_STAT2_XXX_63_48 UINT64_C(0xffff000000000000)
412 #define TXN_STAT2_OCTS UINT64_C(0x0000ffffffffffff)
416 #define TXN_STAT3_XXX_63_48 UINT64_C(0xffffffff00000000)
417 #define TXN_STAT3_PKTS UINT64_C(0x00000000ffffffff)
421 #define TXN_STAT4_HIST1 UINT64_C(0xffffffff00000000)
422 #define TXN_STAT4_HIST0 UINT64_C(0x00000000ffffffff)
426 #define TXN_STAT5_HIST3 UINT64_C(0xffffffff00000000)
427 #define TXN_STAT5_HIST2 UINT64_C(0x00000000ffffffff)
431 #define TXN_STAT6_HIST5 UINT64_C(0xffffffff00000000)
432 #define TXN_STAT6_HIST4 UINT64_C(0x00000000ffffffff)
436 #define TXN_STAT7_HIST7 UINT64_C(0xffffffff00000000)
437 UINT64_C(0x00000000ffffffff)
441 #define TXN_STAT8_MCST UINT64_C(0xffffffff00000000)
442 #define TXN_STAT8_BCST UINT64_C(0x00000000ffffffff)
446 #define TXN_STAT9_UNDFLW UINT64_C(0xffffffff00000000)
447 #define TXN_STAT9_CTL UINT64_C(0x00000000ffffffff)
451 #define BIST_XXX_63_10 UINT64_C(0xfffffffffffffc00)
452 #define BIST_STATUS UINT64_C(0x00000000000003ff)
456 #define RX_PRTS_XXX_63_3 UINT64_C(0xfffffffffffffff8)
457 #define RX_PRTS_PRTS UINT64_C(0x0000000000000007)
461 #define RX_BP_DROPN_XXX_63_6 UINT64_C(0xffffffffffffffc0)
462 #define RX_BP_DROPN_MARK UINT64_C(0x000000000000003f)
466 #define RX_BP_ONN_XXX_63_9 UINT64_C(0xfffffffffffffe00)
467 #define RX_BP_ONN_MARK UINT64_C(0x00000000000001ff)
471 #define RX_BP_OFFN_XXX_63_6 UINT64_C(0xffffffffffffffc0)
472 #define RX_BP_OFFN_MARK UINT64_C(0x000000000000003f)
476 #define TX_PRTS_XXX_63_5 UINT64_C(0xffffffffffffffe0)
477 #define TX_PRTS_PRTS UINT64_C(0x000000000000001f)
481 #define TX_IFG_XXX_63_8 UINT64_C(0xffffffffffffff00)
482 #define TX_IFG_IFG2 UINT64_C(0x00000000000000f0)
483 #define TX_IFG_IFG1 UINT64_C(0x000000000000000f)
487 #define TX_JAM_XXX_63_8 UINT64_C(0xffffffffffffff00)
488 #define TX_JAM_JAM UINT64_C(0x00000000000000ff)
492 #define TX_COL_ATTEMPT_XXX_63_5 UINT64_C(0xffffffffffffffe0)
493 #define TX_COL_ATTEMPT_LIMIT UINT64_C(0x000000000000001f)
497 #define TX_PAUSE_PKT_DMAC_XXX_63_48 UINT64_C(0xffff000000000000)
498 #define TX_PAUSE_PKT_DMAC_DMAC UINT64_C(0x0000ffffffffffff)
502 #define TX_PAUSE_PKT_TYPE_XXX_63_16 UINT64_C(0xffffffffffff0000)
503 #define TX_PAUSE_PKT_TYPE_TYPE UINT64_C(0x000000000000ffff)
507 #define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000)
508 #define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800)
509 #define TX_OVR_BP_EN UINT64_C(0x0000000000000700)
510 #define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080)
511 #define TX_OVR_BP_BP UINT64_C(0x0000000000000070)
512 #define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008)
513 #define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007)
517 #define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000)
518 #define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800)
519 #define TX_OVR_BP_EN UINT64_C(0x0000000000000700)
520 #define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080)
521 #define TX_OVR_BP_BP UINT64_C(0x0000000000000070)
522 #define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008)
523 #define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007)
527 #define TX_BP_SR_XXX_63_3 UINT64_C(0xfffffffffffffff8)
528 #define TX_BP_SR_BP UINT64_C(0x0000000000000007)
532 #define TX_CORRUPT_XXX_63_3 UINT64_C(0xfffffffffffffff8)
533 #define TX_CORRUPT_CORRUPT UINT64_C(0x0000000000000007)
537 #define RX_PRT_INFO_XXX_63_19 UINT64_C(0xfffffffffff80000)
538 #define RX_PRT_INFO_DROP UINT64_C(0x0000000000070000)
539 #define RX_PRT_INFO_XXX_15_3 UINT64_C(0x000000000000fff8)
540 #define RX_PRT_INFO_COMMIT UINT64_C(0x0000000000000007)
544 #define TX_LFSR_XXX_63_16 UINT64_C(0xffffffffffff0000)
545 #define TX_LFSR_LFSR UINT64_C(0x000000000000ffff)
549 #define TX_INT_REG_XXX_63_20 UINT64_C(0xfffffffffff00000)
550 #define TX_INT_REG_XXX_19 UINT64_C(0x0000000000080000)
551 #define TX_INT_REG_LATE_COL UINT64_C(0x0000000000070000)
552 #define TX_INT_REG_XXX_15 UINT64_C(0x0000000000008000)
553 #define TX_INT_REG_XSDEF UINT64_C(0x0000000000007000)
554 #define TX_INT_REG_XXX_11 UINT64_C(0x0000000000000800)
555 #define TX_INT_REG_XSCOL UINT64_C(0x0000000000000700)
556 #define TX_INT_REG_XXX_7_5 UINT64_C(0x00000000000000e0)
557 #define TX_INT_REG_UNDFLW UINT64_C(0x000000000000001c)
558 #define TX_INT_REG_XXX_1 UINT64_C(0x0000000000000002)
559 #define TX_INT_REG_PKO_NXA UINT64_C(0x0000000000000001)
563 #define TX_INT_EN_XXX_63_20 UINT64_C(0xfffffffffff00000)
564 #define TX_INT_EN_XXX_19 UINT64_C(0x0000000000080000)
565 #define TX_INT_EN_LATE_COL UINT64_C(0x0000000000070000)
566 #define TX_INT_EN_XXX_15 UINT64_C(0x0000000000008000)
567 #define TX_INT_EN_XSDEF UINT64_C(0x0000000000007000)
568 #define TX_INT_EN_XXX_11 UINT64_C(0x0000000000000800)
569 #define TX_INT_EN_XSCOL UINT64_C(0x0000000000000700)
570 #define TX_INT_EN_XXX_7_5 UINT64_C(0x00000000000000e0)
571 #define TX_INT_EN_UNDFLW UINT64_C(0x000000000000001c)
572 #define TX_INT_EN_XXX_1 UINT64_C(0x0000000000000002)
573 #define TX_INT_EN_PKO_NXA UINT64_C(0x0000000000000001)
577 #define NXA_ADR_XXX_63_6 UINT64_C(0xffffffffffffffc0)
578 #define NXA_ADR_PRT UINT64_C(0x000000000000003f)
582 #define BAD_REG_XXX_63_31 UINT64_C(0xffffffff80000000)
583 #define BAD_REG_INB_NXA UINT64_C(0x0000000078000000)
584 #define BAD_REG_STATOVR UINT64_C(0x0000000004000000)
585 #define BAD_REG_XXX_25 UINT64_C(0x0000000002000000)
586 #define BAD_REG_LOSTSTAT UINT64_C(0x0000000001c00000)
587 #define BAD_REG_XXX_21_18 UINT64_C(0x00000000003c0000)
588 #define BAD_REG_XXX_17_5 UINT64_C(0x000000000003ffe0)
589 #define BAD_REG_OUT_OVR UINT64_C(0x000000000000001c)
590 #define BAD_REG_XXX_1_0 UINT64_C(0x0000000000000003)
594 #define STAT_BP_XXX_63_17 UINT64_C(0xfffffffffffe0000)
595 #define STAT_BP_BP UINT64_C(0x0000000000010000)
596 #define STAT_BP_CNT UINT64_C(0x000000000000ffff)
600 #define TX_CLK_MSKN_XXX_63_1 UINT64_C(0xfffffffffffffffe)
601 #define TX_CLK_MSKN_MSK UINT64_C(0x0000000000000001)
605 #define RX_TX_STATUS_XXX_63_7 UINT64_C(0xffffffffffffff80)
606 #define RX_TX_STATUS_TX UINT64_C(0x0000000000000070)
607 #define RX_TX_STATUS_XXX_3 UINT64_C(0x0000000000000008)
608 #define RX_TX_STATUS_RX UINT64_C(0x0000000000000007)
612 #define INF_MODE_XXX_63_3 UINT64_C(0xfffffffffffffff8)
613 #define INF_MODE_P0MII UINT64_C(0x0000000000000004)
614 #define INF_MODE_EN UINT64_C(0x0000000000000002)
615 #define INF_MODE_TYPE UINT64_C(0x0000000000000001)
617 #define INF_MODE_MODE UINT64_C(0x0000000000000070)
618 #define INF_MODE_MODE_SGMII UINT64_C(0x0000000000000020)
619 #define INF_MODE_MODE_XAUI UINT64_C(0x0000000000000030)
621 #define MIO_QLM_CFG(x) (UINT64_C(0x0001180000001590) + (x)*8)
623 #define MIO_QLM_CFG_CFG UINT64_C(0x000000000000000f)
637 #define GMX0_BASE_PORT0 UINT64_C(0x0001180008000000)
649 #define PCS_BASE(g, i) (UINT64_C(0x00011800b0001000) + 0x8000000 * (g) + 0x400 * (i))
657 #define PCS_MR_CONTROL_RES_16_63 UINT64_C(0xffffffffffff0000)
658 #define PCS_MR_CONTROL_RESET UINT64_C(0x0000000000008000)
659 #define PCS_MR_CONTROL_LOOPBCK1 UINT64_C(0x0000000000004000)
660 #define PCS_MR_CONTROL_SPDLSB UINT64_C(0x0000000000002000)
661 #define PCS_MR_CONTROL_AN_EN UINT64_C(0x0000000000001000)
662 #define PCS_MR_CONTROL_PWR_DN UINT64_C(0x0000000000000800)
663 #define PCS_MR_CONTROL_RES_10_10 UINT64_C(0x0000000000000400)
664 #define PCS_MR_CONTROL_RST_AN UINT64_C(0x0000000000000200)
665 #define PCS_MR_CONTROL_DUPLEX UINT64_C(0x0000000000000100)
666 #define PCS_MR_CONTROL_COLTST UINT64_C(0x0000000000000080)
667 #define PCS_MR_CONTROL_SPDMSB UINT64_C(0x0000000000000040)
668 #define PCS_MR_CONTROL_UNI UINT64_C(0x0000000000000020)
669 #define PCS_MR_CONTROL_RES_0_4 UINT64_C(0x000000000000001f)
671 #define PCS_MR_STATUS_RES_16_63 UINT64_C(0xffffffffffff0000)
672 #define PCS_MR_STATUS_HUN_T4 UINT64_C(0x0000000000008000)
673 #define PCS_MR_STATUS_HUN_XFD UINT64_C(0x0000000000004000)
674 #define PCS_MR_STATUS_HUN_XHD UINT64_C(0x0000000000002000)
675 #define PCS_MR_STATUS_TEN_FD UINT64_C(0x0000000000001000)
676 #define PCS_MR_STATUS_TEN_HD UINT64_C(0x0000000000000800)
677 #define PCS_MR_STATUS_HUN_T2FD UINT64_C(0x0000000000000400)
678 #define PCS_MR_STATUS_HUN_T2HD UINT64_C(0x0000000000000200)
679 #define PCS_MR_STATUS_EXT_ST UINT64_C(0x0000000000000100)
680 #define PCS_MR_STATUS_RES_7_7 UINT64_C(0x0000000000000080)
681 #define PCS_MR_STATUS_PRB_SUP UINT64_C(0x0000000000000040)
682 #define PCS_MR_STATUS_AN_CPT UINT64_C(0x0000000000000020)
683 #define PCS_MR_STATUS_RM_FLT UINT64_C(0x0000000000000010)
684 #define PCS_MR_STATUS_AN_ABIL UINT64_C(0x0000000000000008)
685 #define PCS_MR_STATUS_LNK_ST UINT64_C(0x0000000000000004)
686 #define PCS_MR_STATUS_RES_1_1 UINT64_C(0x0000000000000002)
687 #define PCS_MR_STATUS_EXTND UINT64_C(0x0000000000000001)
689 #define PCS_LINK_TIMER_COUNT_MASK UINT64_C(0x000000000000ffff)
691 #define PCS_MISC_CTL_SGMII UINT64_C(0x0000000000001000)
692 #define PCS_MISC_CTL_GMXENO UINT64_C(0x0000000000000800)
693 #define PCS_MISC_CTL_LOOPBCK2 UINT64_C(0x0000000000000400)
694 #define PCS_MISC_CTL_MAC_PHY UINT64_C(0x0000000000000200)
695 #define PCS_MISC_CTL_MODE UINT64_C(0x0000000000000100)
696 #define PCS_MISC_CTL_AN_OVRD UINT64_C(0x0000000000000080)
697 #define PCS_MISC_CTL_SAMP_PT UINT64_C(0x000000000000007f)
Indexes created Sat Nov 08 12:09:53 GMT 2025