Cross Reference: /src/sys/arch/mips/cavium/dev/octeon

Lines Matching refs:pin
114 	 * Device trees give a 0x100 window but the extended pin
125 	 * Set the pin count and the register layout per the SDK CSR
187 octgpio_cfg_reg(struct octgpio_softc *sc, uint32_t pin)
190 	if (pin >= sc->sc_xbit)
191 		return GPIO_XBIT_CFG16_OFFSET + (pin - sc->sc_xbit) * 8;
192 	return GPIO_BIT_CFG0_OFFSET + pin * 8;
196 octgpio_pin_ctl(struct octgpio_softc *sc, uint32_t pin, int flags)
201 	KASSERT(pin < sc->sc_npins);
202 	reg = octgpio_cfg_reg(sc, pin);
228 	struct octgpio_pin *pin;
232 	/* #gpio-cells = <2>: controller phandle, pin, flags. */
243 	pin = kmem_zalloc(sizeof(*pin), KM_SLEEP);
244 	pin->pin_sc = sc;
245 	pin->pin_no = pinno;
246 	pin->pin_actlo = actlo;
248 	return pin;
255 	struct octgpio_pin *pin = priv;
257 	octgpio_pin_ctl(sc, pin->pin_no, GPIO_PIN_INPUT);
258 	kmem_free(pin, sizeof(*pin));
264 	struct octgpio_pin *pin = priv;
265 	struct octgpio_softc *sc = pin->pin_sc;
268 	val = (GPIO_RD_8(sc, GPIO_RX_DAT_OFFSET) >> pin->pin_no) & 1;
269 	if (!raw && pin->pin_actlo)
278 	struct octgpio_pin *pin = priv;
279 	struct octgpio_softc *sc = pin->pin_sc;
281 	if (!raw && pin->pin_actlo)
285 		GPIO_WR_8(sc, GPIO_TX_SET_OFFSET, 1ull << pin->pin_no);
287 		GPIO_WR_8(sc, GPIO_TX_CLR_OFFSET, 1ull << pin->pin_no);
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