Lines Matching refs:UINT64_C
79 #define NPI_RSL_INT_BLOCKS_XXX_63_31 UINT64_C(0xffffffff80000000)
80 #define NPI_RSL_INT_BLOCKS_IOB UINT64_C(0x0000000040000000)
81 #define NPI_RSL_INT_BLOCKS_XXX_29_23 UINT64_C(0x000000003f800000)
82 #define NPI_RSL_INT_BLOCKS_ASX0 UINT64_C(0x0000000000400000)
83 #define NPI_RSL_INT_BLOCKS_XXX_21 UINT64_C(0x0000000000200000)
84 #define NPI_RSL_INT_BLOCKS_PIP UINT64_C(0x0000000000100000)
85 #define NPI_RSL_INT_BLOCKS_XXX_19_18 UINT64_C(0x00000000000c0000)
86 #define NPI_RSL_INT_BLOCKS_LMC UINT64_C(0x0000000000020000)
87 #define NPI_RSL_INT_BLOCKS_L2C UINT64_C(0x0000000000010000)
88 #define NPI_RSL_INT_BLOCKS_XXX_15_13 UINT64_C(0x000000000000e000)
89 #define NPI_RSL_INT_BLOCKS_POW UINT64_C(0x0000000000001000)
90 #define NPI_RSL_INT_BLOCKS_TIM UINT64_C(0x0000000000000800)
91 #define NPI_RSL_INT_BLOCKS_PKO UINT64_C(0x0000000000000400)
92 #define NPI_RSL_INT_BLOCKS_IPD UINT64_C(0x0000000000000200)
93 #define NPI_RSL_INT_BLOCKS_XXX_8_6 UINT64_C(0x00000000000001c0)
94 #define NPI_RSL_INT_BLOCKS_FPA UINT64_C(0x0000000000000020)
95 #define NPI_RSL_INT_BLOCKS_XXX_4 UINT64_C(0x0000000000000010)
96 #define NPI_RSL_INT_BLOCKS_NPI UINT64_C(0x0000000000000008)
97 #define NPI_RSL_INT_BLOCKS_GMX1 UINT64_C(0x0000000000000004)
98 #define NPI_RSL_INT_BLOCKS_GMX0 UINT64_C(0x0000000000000002)
99 #define NPI_RSL_INT_BLOCKS_MIO UINT64_C(0x0000000000000001)
101 #define NPI_DBG_SELECT_XXX_63_16 UINT64_C(0xffffffffffff0000)
102 #define NPI_DBG_SELECT_DBG_SEL UINT64_C(0x000000000000ffff)
104 #define NPI_CTL_STATUS_XXX_63 UINT64_C(0x8000000000000000)
105 #define NPI_DBG_SELECT_DBG_SEL UINT64_C(0x000000000000ffff)
107 #define NPI_CTL_STATUS_XXX_63 UINT64_C(0x8000000000000000)
108 #define NPI_CTL_STATUS_CHIP_REV UINT64_C(0x7f80000000000000)
109 #define NPI_CTL_STATUS_DIS_PNIW UINT64_C(0x0040000000000000)
110 #define NPI_CTL_STATUS_SPR5 UINT64_C(0x0020000000000000)
111 #define NPI_CTL_STATUS_SPR4 UINT64_C(0x0010000000000000)
112 #define NPI_CTL_STATUS_SPR8 UINT64_C(0x0008000000000000)
113 #define NPI_CTL_STATUS_OUT0_ENB UINT64_C(0x0004000000000000)
114 #define NPI_CTL_STATUS_SPR3 UINT64_C(0x0002000000000000)
115 #define NPI_CTL_STATUS_SPR2 UINT64_C(0x0001000000000000)
116 #define NPI_CTL_STATUS_SPR7 UINT64_C(0x0000800000000000)
117 #define NPI_CTL_STATUS_INS0_ENB UINT64_C(0x0000400000000000)
118 #define NPI_CTL_STATUS_SPR1 UINT64_C(0x0000200000000000)
119 #define NPI_CTL_STATUS_SPR0 UINT64_C(0x0000100000000000)
120 #define NPI_CTL_STATUS_SPR6 UINT64_C(0x0000080000000000)
121 #define NPI_CTL_STATUS_INS0_64B UINT64_C(0x0000040000000000)
122 #define NPI_CTL_STATUS_PCI_WDIS UINT64_C(0x0000020000000000)
123 #define NPI_CTL_STATUS_WAIT_COM UINT64_C(0x0000010000000000)
124 #define NPI_CTL_STATUS_SPARES1 UINT64_C(0x000000e000000000)
125 #define NPI_CTL_STATUS_MAX_WORD UINT64_C(0x0000001f00000000)
126 #define NPI_CTL_STATUS_SPARES0 UINT64_C(0x00000000fffffc00)
127 #define NPI_CTL_STATUS_TIMER UINT64_C(0x00000000000003ff)
129 #define NPI_INT_SUM_XXX_63_62 UINT64_C(0xc000000000000000)
130 #define NPI_INT_SUM_Q1_A_F UINT64_C(0x2000000000000000)
131 #define NPI_INT_SUM_Q1_S_E UINT64_C(0x1000000000000000)
132 #define NPI_INT_SUM_PDF_P_F UINT64_C(0x0800000000000000)
133 #define NPI_INT_SUM_PDF_P_E UINT64_C(0x0400000000000000)
134 #define NPI_INT_SUM_PCF_P_F UINT64_C(0x0200000000000000)
135 #define NPI_INT_SUM_PCF_P_E UINT64_C(0x0100000000000000)
136 #define NPI_INT_SUM_RDX_S_E UINT64_C(0x0080000000000000)
137 #define NPI_INT_SUM_RWX_S_E UINT64_C(0x0040000000000000)
138 #define NPI_INT_SUM_PNC_A_F UINT64_C(0x0020000000000000)
139 #define NPI_INT_SUM_PNC_S_F UINT64_C(0x0010000000000000)
140 #define NPI_INT_SUM_COM_A_F UINT64_C(0x0008000000000000)
141 #define NPI_INT_SUM_COM_S_E UINT64_C(0x0004000000000000)
142 #define NPI_INT_SUM_Q3_A_F UINT64_C(0x0002000000000000)
143 #define NPI_INT_SUM_Q3_S_E UINT64_C(0x0001000000000000)
144 #define NPI_INT_SUM_Q2_A_F UINT64_C(0x0000800000000000)
145 #define NPI_INT_SUM_Q2_S_E UINT64_C(0x0000400000000000)
146 #define NPI_INT_SUM_PCR_A_F UINT64_C(0x0000200000000000)
147 #define NPI_INT_SUM_PCR_S_E UINT64_C(0x0000100000000000)
148 #define NPI_INT_SUM_FCR_A_F UINT64_C(0x0000080000000000)
149 #define NPI_INT_SUM_FCR_S_E UINT64_C(0x0000040000000000)
150 #define NPI_INT_SUM_IOBDMA UINT64_C(0x0000020000000000)
151 #define NPI_INT_SUM_P_DPERR UINT64_C(0x0000010000000000)
152 #define NPI_INT_SUM_WIN_RTO UINT64_C(0x0000008000000000)
153 #define NPI_INT_SUM_SPR17 UINT64_C(0x0000004000000000)
154 #define NPI_INT_SUM_SPR16 UINT64_C(0x0000002000000000)
155 #define NPI_INT_SUM_SPR26 UINT64_C(0x0000001000000000)
156 #define NPI_INT_SUM_IO_PPERR UINT64_C(0x0000000800000000)
157 #define NPI_INT_SUM_SPR15 UINT64_C(0x0000000400000000)
158 #define NPI_INT_SUM_SPR14 UINT64_C(0x0000000200000000)
159 #define NPI_INT_SUM_SPR25 UINT64_C(0x0000000100000000)
160 #define NPI_INT_SUM_P0_PTOUT UINT64_C(0x0000000080000000)
161 #define NPI_INT_SUM_SPR13 UINT64_C(0x0000000040000000)
162 #define NPI_INT_SUM_SPR12 UINT64_C(0x0000000020000000)
163 #define NPI_INT_SUM_SPR24 UINT64_C(0x0000000010000000)
164 #define NPI_INT_SUM_P0_PPERR UINT64_C(0x0000000008000000)
165 #define NPI_INT_SUM_SPR11 UINT64_C(0x0000000004000000)
166 #define NPI_INT_SUM_SPR10 UINT64_C(0x0000000002000000)
167 #define NPI_INT_SUM_SPR23 UINT64_C(0x0000000001000000)
168 #define NPI_INT_SUM_G0_RTOUT UINT64_C(0x0000000000800000)
169 #define NPI_INT_SUM_SPR9 UINT64_C(0x0000000000400000)
170 #define NPI_INT_SUM_SPR8 UINT64_C(0x0000000000200000)
171 #define NPI_INT_SUM_SPR22 UINT64_C(0x0000000000100000)
172 #define NPI_INT_SUM_P0_PERR UINT64_C(0x0000000000080000)
173 #define NPI_INT_SUM_SPR7 UINT64_C(0x0000000000040000)
174 #define NPI_INT_SUM_SPR6 UINT64_C(0x0000000000020000)
175 #define NPI_INT_SUM_SPR21 UINT64_C(0x0000000000010000)
176 #define NPI_INT_SUM_P0_RTOUT UINT64_C(0x0000000000008000)
177 #define NPI_INT_SUM_SPR5 UINT64_C(0x0000000000004000)
178 #define NPI_INT_SUM_SPR4 UINT64_C(0x0000000000002000)
179 #define NPI_INT_SUM_SPR20 UINT64_C(0x0000000000001000)
180 #define NPI_INT_SUM_IO_OVERF UINT64_C(0x0000000000000800)
181 #define NPI_INT_SUM_SPR3 UINT64_C(0x0000000000000400)
182 #define NPI_INT_SUM_SPR2 UINT64_C(0x0000000000000200)
183 #define NPI_INT_SUM_SPR19 UINT64_C(0x0000000000000100)
184 #define NPI_INT_SUM_IO_RTOUT UINT64_C(0x0000000000000080)
185 #define NPI_INT_SUM_SPR1 UINT64_C(0x0000000000000040)
186 #define NPI_INT_SUM_SPR0 UINT64_C(0x0000000000000020)
187 #define NPI_INT_SUM_SPR18 UINT64_C(0x0000000000000010)
188 #define NPI_INT_SUM_PO0_2SML UINT64_C(0x0000000000000008)
189 #define NPI_INT_SUM_PCI_RSL UINT64_C(0x0000000000000004)
190 #define NPI_INT_SUM_RML_TWO UINT64_C(0x0000000000000002)
191 #define NPI_INT_SUM_RML_RTO UINT64_C(0x0000000000000001)
193 #define NPI_INT_ENB_XXX_63_62 UINT64_C(0xc000000000000000)
194 #define NPI_INT_ENB_Q1_A_F UINT64_C(0x2000000000000000)
195 #define NPI_INT_ENB_Q1_S_E UINT64_C(0x1000000000000000)
196 #define NPI_INT_ENB_PDF_P_F UINT64_C(0x0800000000000000)
197 #define NPI_INT_ENB_PDF_P_E UINT64_C(0x0400000000000000)
198 #define NPI_INT_ENB_PCF_P_F UINT64_C(0x0200000000000000)
199 #define NPI_INT_ENB_PCF_P_E UINT64_C(0x0100000000000000)
200 #define NPI_INT_ENB_RDX_S_E UINT64_C(0x0080000000000000)
201 #define NPI_INT_ENB_RWX_S_E UINT64_C(0x0040000000000000)
202 #define NPI_INT_ENB_PNC_A_F UINT64_C(0x0020000000000000)
203 #define NPI_INT_ENB_PNC_S_F UINT64_C(0x0010000000000000)
204 #define NPI_INT_ENB_COM_A_F UINT64_C(0x0008000000000000)
205 #define NPI_INT_ENB_COM_S_E UINT64_C(0x0004000000000000)
206 #define NPI_INT_ENB_Q3_A_F UINT64_C(0x0002000000000000)
207 #define NPI_INT_ENB_Q3_S_E UINT64_C(0x0001000000000000)
208 #define NPI_INT_ENB_Q2_A_F UINT64_C(0x0000800000000000)
209 #define NPI_INT_ENB_Q2_S_E UINT64_C(0x0000400000000000)
210 #define NPI_INT_ENB_PCR_A_F UINT64_C(0x0000200000000000)
211 #define NPI_INT_ENB_PCR_S_E UINT64_C(0x0000100000000000)
212 #define NPI_INT_ENB_FCR_A_F UINT64_C(0x0000080000000000)
213 #define NPI_INT_ENB_FCR_S_E UINT64_C(0x0000040000000000)
214 #define NPI_INT_ENB_IOBDMA UINT64_C(0x0000020000000000)
215 #define NPI_INT_ENB_P_DPERR UINT64_C(0x0000010000000000)
216 #define NPI_INT_ENB_WIN_RTO UINT64_C(0x0000008000000000)
217 #define NPI_INT_ENB_SPR17 UINT64_C(0x0000004000000000)
218 #define NPI_INT_ENB_SPR16 UINT64_C(0x0000002000000000)
219 #define NPI_INT_ENB_SPR26 UINT64_C(0x0000001000000000)
220 #define NPI_INT_ENB_IO_PPERR UINT64_C(0x0000000800000000)
221 #define NPI_INT_ENB_SPR15 UINT64_C(0x0000000400000000)
222 #define NPI_INT_ENB_SPR14 UINT64_C(0x0000000200000000)
223 #define NPI_INT_ENB_SPR25 UINT64_C(0x0000000100000000)
224 #define NPI_INT_ENB_P0_PTOUT UINT64_C(0x0000000080000000)
225 #define NPI_INT_ENB_SPR13 UINT64_C(0x0000000040000000)
226 #define NPI_INT_ENB_SPR12 UINT64_C(0x0000000020000000)
227 #define NPI_INT_ENB_SPR24 UINT64_C(0x0000000010000000)
228 #define NPI_INT_ENB_P0_PPERR UINT64_C(0x0000000008000000)
229 #define NPI_INT_ENB_SPR11 UINT64_C(0x0000000004000000)
230 #define NPI_INT_ENB_SPR10 UINT64_C(0x0000000002000000)
231 #define NPI_INT_ENB_SPR23 UINT64_C(0x0000000001000000)
232 #define NPI_INT_ENB_G0_RTOUT UINT64_C(0x0000000000800000)
233 #define NPI_INT_ENB_SPR9 UINT64_C(0x0000000000400000)
234 #define NPI_INT_ENB_SPR8 UINT64_C(0x0000000000200000)
235 #define NPI_INT_ENB_SPR22 UINT64_C(0x0000000000100000)
236 #define NPI_INT_ENB_P0_PERR UINT64_C(0x0000000000080000)
237 #define NPI_INT_ENB_SPR7 UINT64_C(0x0000000000040000)
238 #define NPI_INT_ENB_SPR6 UINT64_C(0x0000000000020000)
239 #define NPI_INT_ENB_SPR21 UINT64_C(0x0000000000010000)
240 #define NPI_INT_ENB_P0_RTOUT UINT64_C(0x0000000000008000)
241 #define NPI_INT_ENB_SPR5 UINT64_C(0x0000000000004000)
242 #define NPI_INT_ENB_SPR4 UINT64_C(0x0000000000002000)
243 #define NPI_INT_ENB_SPR20 UINT64_C(0x0000000000001000)
244 #define NPI_INT_ENB_IO_OVERF UINT64_C(0x0000000000000800)
245 #define NPI_INT_ENB_SPR3 UINT64_C(0x0000000000000400)
246 #define NPI_INT_ENB_SPR2 UINT64_C(0x0000000000000200)
247 #define NPI_INT_ENB_SPR19 UINT64_C(0x0000000000000100)
248 #define NPI_INT_ENB_IO_RTOUT UINT64_C(0x0000000000000080)
249 #define NPI_INT_ENB_SPR1 UINT64_C(0x0000000000000040)
250 #define NPI_INT_ENB_SPR0 UINT64_C(0x0000000000000020)
251 #define NPI_INT_ENB_SPR18 UINT64_C(0x0000000000000010)
252 #define NPI_INT_ENB_PO0_2SML UINT64_C(0x0000000000000008)
253 #define NPI_INT_ENB_PCI_RSL UINT64_C(0x0000000000000004)
254 #define NPI_INT_ENB_RML_TWO UINT64_C(0x0000000000000002)
255 #define NPI_INT_ENB_RML_RTO UINT64_C(0x0000000000000001)
257 #define NPI_MEM_ACCESS_SUBIDX_XXX_63_38 UINT64_C(0xffffffc000000000)
258 #define NPI_MEM_ACCESS_SUBIDX_SHORT UINT64_C(0x0000002000000000)
259 #define NPI_MEM_ACCESS_SUBIDX_NMERGE UINT64_C(0x0000001000000000)
260 #define NPI_MEM_ACCESS_SUBIDX_ESR UINT64_C(0x0000000c00000000)
261 #define NPI_MEM_ACCESS_SUBIDX_ESW UINT64_C(0x0000000300000000)
262 #define NPI_MEM_ACCESS_SUBIDX_NSR UINT64_C(0x0000000080000000)
263 #define NPI_MEM_ACCESS_SUBIDX_NSW UINT64_C(0x0000000040000000)
264 #define NPI_MEM_ACCESS_SUBIDX_ROR UINT64_C(0x0000000020000000)
265 #define NPI_MEM_ACCESS_SUBIDX_ROW UINT64_C(0x0000000010000000)
266 #define NPI_MEM_ACCESS_SUBIDX_BA UINT64_C(0x000000000fffffff)
268 #define NPI_PCI_READ_CMD_XXX_63_11 UINT64_C(0xfffffffffffff800)
269 #define NPI_PCI_READ_CMD_CMD_SIZE UINT64_C(0x00000000000007ff)
271 #define NPI_NUM_DESC_OUTPUT0_XXX_63_32 UINT64_C(0xffffffff00000000)
272 #define NPI_NUM_DESC_OUTPUT0_SIZE UINT64_C(0x00000000ffffffff)
274 #define NPI_BASE_ADDR_INPUT0_BADDR UINT64_C(0xfffffffffffffff8)
275 #define NPI_BASE_ADDR_INPUT0_XXX_2_0 UINT64_C(0x0000000000000007)
277 #define NPI_SIZE_INPUT0_XXX_63_32 UINT64_C(0xffffffff00000000)
278 #define NPI_SIZE_INPUT0_SIZE UINT64_C(0x00000000ffffffff)
280 #define PCI_READ_TIMEOUT_XXX_63_32 UINT64_C(0xffffffff00000000)
281 #define PCI_READ_TIMEOUT_ENB UINT64_C(0x0000000080000000)
282 #define PCI_READ_TIMEOUT_CNT UINT64_C(0x000000007fffffff)
284 #define NPI_BASE_ADDR_OUTPUT0_BADDR UINT64_C(0xfffffffffffffff8)
285 #define NPI_BASE_ADDR_OUTPUT0_XXX_2_0 UINT64_C(0x0000000000000007)
287 #define NPI_PCI_BURST_SIZE_XXX_63_14 UINT64_C(0xffffffffffffc000)
288 #define NPI_PCI_BURST_SIZE_WR_BRST UINT64_C(0x0000000000003f80)
289 #define NPI_PCI_BURST_SIZE_RD_BRST UINT64_C(0x000000000000007f)
291 #define NPI_BUFF_SIZE_OUTPUT0_XXX_63_23 UINT64_C(0xffffffffff800000)
292 #define NPI_BUFF_SIZE_OUTPUT0_ISIZE UINT64_C(0x00000000007f0000)
293 #define NPI_BUFF_SIZE_OUTPUT0_BSIZE UINT64_C(0x000000000000ffff)
295 #define NPI_OUTPUT_CONTROL_XXX_63_48 UINT64_C(0xffff000000000000)
296 #define NPI_OUTPUT_CONTROL_SPR5 UINT64_C(0x0000e00000000000)
297 #define NPI_OUTPUT_CONTROL_P0_BMODE UINT64_C(0x0000100000000000)
298 #define NPI_OUTPUT_CONTROL_SPR4 UINT64_C(0x00000fff00000000)
299 #define NPI_OUTPUT_CONTROL_O0_ES UINT64_C(0x00000000c0000000)
300 #define NPI_OUTPUT_CONTROL_O0_NS UINT64_C(0x0000000020000000)
301 #define NPI_OUTPUT_CONTROL_O0_RO UINT64_C(0x0000000010000000)
302 #define NPI_OUTPUT_CONTROL_SPR3 UINT64_C(0x000000000e000000)
303 #define NPI_OUTPUT_CONTROL_O0_CSRM UINT64_C(0x0000000001000000)
304 #define NPI_OUTPUT_CONTROL_SPR2 UINT64_C(0x0000000000f00000)
305 #define NPI_OUTPUT_CONTROL_SPR1 UINT64_C(0x00000000000e0000)
306 #define NPI_OUTPUT_CONTROL_IPTR_O0 UINT64_C(0x0000000000010000)
307 UINT64_C(0x000000000000fff0)
308 #define NPI_OUTPUT_CONTROL_ESR_SL0 UINT64_C(0x000000000000000c)
309 #define NPI_OUTPUT_CONTROL_NSR_SL0 UINT64_C(0x0000000000000002)
310 #define NPI_OUTPUT_CONTROL_ROR_SL0 UINT64_C(0x0000000000000001)
312 #define NPI_LOWP_IBUFF_SADDR_XXX_63_36 UINT64_C(0xfffffff000000000)
313 #define NPI_LOWP_IBUFF_SADDR_SADDR UINT64_C(0x0000000fffffffff)
315 #define NPI_HIGHP_IBUFF_SADDR_XXX_63_36 UINT64_C(0xfffffff000000000)
316 #define NPI_HIGHP_IBUFF_SADDR_SADDR UINT64_C(0x0000000fffffffff)
318 #define NPI_LOWP_DBELL_XXX_63_16 UINT64_C(0xffffffffffff0000)
319 #define NPI_LOWP_DBELL_DBELL UINT64_C(0x000000000000ffff)
321 #define NPI_HIGHP_DBELL_XXX_63_16 UINT64_C(0xffffffffffff0000)
322 #define NPI_HIGHP_DBELL_DBELL UINT64_C(0x000000000000ffff)
324 #define NPI_DMA_CONTROL_XXX_63_36 UINT64_C(0xfffffff000000000)
325 #define NPI_DMA_CONTROL_B0_LEND UINT64_C(0x0000000800000000)
326 #define NPI_DMA_CONTROL_DWB_DENB UINT64_C(0x0000000400000000)
327 #define NPI_DMA_CONTROL_DWB_ICHK UINT64_C(0x00000003fe000000)
328 #define NPI_DMA_CONTROL_FPA_QUE UINT64_C(0x0000000001c00000)
329 #define NPI_DMA_CONTROL_O_ADD1 UINT64_C(0x0000000000200000)
330 #define NPI_DMA_CONTROL_O_RO UINT64_C(0x0000000000100000)
331 #define NPI_DMA_CONTROL_O_NS UINT64_C(0x0000000000080000)
332 #define NPI_DMA_CONTROL_O_ES UINT64_C(0x0000000000060000)
333 #define NPI_DMA_CONTROL_O_MODE UINT64_C(0x0000000000010000)
334 #define NPI_DMA_CONTROL_HP_ENB UINT64_C(0x0000000000008000)
335 #define NPI_DMA_CONTROL_LP_ENB UINT64_C(0x0000000000004000)
336 #define NPI_DMA_CONTROL_CSIZE UINT64_C(0x0000000000003fff)
338 #define NPI_PCI_INT_ARB_CFG_XXX_63_5 UINT64_C(0xffffffffffffffe0)
339 #define NPI_PCI_INT_ARB_CFG_EN UINT64_C(0x0000000000000010)
340 #define NPI_PCI_INT_ARB_CFG_PARK_MOD UINT64_C(0x0000000000000008)
341 #define NPI_PCI_INT_ARB_CFG_PARK_DEV UINT64_C(0x0000000000000007)
343 #define NPI_INPUT_CONTROL_XXX_63_22 UINT64_C(0xffffffffffc00000)
344 #define NPI_INPUT_CONTROL_PBP_DHI UINT64_C(0x00000000003ffe00)
345 #define NPI_INPUT_CONTROL_D_NSR UINT64_C(0x0000000000000100)
346 #define NPI_INPUT_CONTROL_D_ESR UINT64_C(0x00000000000000c0)
347 #define NPI_INPUT_CONTROL_D_ROR UINT64_C(0x0000000000000020)
348 #define NPI_INPUT_CONTROL_USE_CSR UINT64_C(0x0000000000000010)
349 #define NPI_INPUT_CONTROL_NSR UINT64_C(0x0000000000000008)
350 #define NPI_INPUT_CONTROL_ESR UINT64_C(0x0000000000000006)
351 #define NPI_INPUT_CONTROL_ROR UINT64_C(0x0000000000000001)
353 #define NPI_DMA_LOWP_COUNTS_XXX_63_39 UINT64_C(0xffffff8000000000)
354 #define NPI_DMA_LOWP_COUNTS_FCNT UINT64_C(0x0000007f00000000)
355 #define NPI_DMA_LOWP_COUNTS_DBELL UINT64_C(0x00000000ffffffff)
357 #define NPI_DMA_HIGHP_COUNTS_XXX_63_39 UINT64_C(0xffffff8000000000)
358 #define NPI_DMA_HIGHP_COUNTS_FCNT UINT64_C(0x0000007f00000000)
359 #define NPI_DMA_HIGHP_COUNTS_DBELL UINT64_C(0x00000000ffffffff)
361 #define NPI_DMA_LOWP_NADDR_XXX_63_40 UINT64_C(0xffffff0000000000)
362 #define NPI_DMA_LOWP_NADDR_STATE UINT64_C(0x000000f000000000)
363 #define NPI_DMA_LOWP_NADDR_ADDR UINT64_C(0x0000000fffffffff)
365 #define NPI_DMA_HIGHP_NADDR_XXX_63_40 UINT64_C(0xffffff0000000000)
366 #define NPI_DMA_HIGHP_NADDR_STATE UINT64_C(0x000000f000000000)
367 #define NPI_DMA_HIGHP_NADDR_ADDR UINT64_C(0x0000000fffffffff)
369 #define NPI_P0_PAIR_CNTS_XXX_63_37 UINT64_C(0xffffffe000000000)
370 #define NPI_P0_PAIR_CNTS_FCNT UINT64_C(0xffffffff00000000)
371 #define NPI_P0_PAIR_CNTS_AVAIL UINT64_C(0x00000000c0000000)
373 #define NPI_P0_DBPAIR_ADDR_XXX_63 UINT64_C(0x8000000000000000)
374 #define NPI_P0_DBPAIR_ADDR_STATE UINT64_C(0x6000000000000000)
375 #define NPI_P0_DBPAIR_ADDR_NADDR UINT64_C(0x1fffffffffffffff)
377 #define NPI_P0_INSTR_CNTS_XXX_63_38 UINT64_C(0xffffffc000000000)
378 #define NPI_P0_INSTR_CNTS_FCNT UINT64_C(0x0000003f00000000)
379 #define NPI_P0_INSTR_CNTS_AVAIL UINT64_C(0x00000000ffffffff)
381 #define NPI_P0_INSTR_ADDR_STATE UINT64_C(0xe000000000000000)
382 #define NPI_P0_INSTR_ADDR_NADDR UINT64_C(0x1fffffffffffffff)
384 #define NPI_WIN_READ_TO_XXX_63_32 UINT64_C(0xffffffff00000000)
385 #define NPI_WIN_READ_TO_TIME UINT64_C(0x00000000ffffffff)
387 #define DBG_DATA_XXX_63_31 UINT64_C(0xffffffff80000000)
388 #define DBG_DATA_PLL_MUL UINT64_C(0x0000000070000000)
389 #define DBG_DATA_XXX_27_23 UINT64_C(0x000000000f800000)
390 #define DBG_DATA_C_MUL UINT64_C(0x00000000007c0000)
391 #define DBG_DATA_DSEL_EXT UINT64_C(0x0000000000020000)
392 #define DBG_DATA_DATA UINT64_C(0x000000000001ffff)
394 #define NPI_PORT_BP_CONTROL_XXX_63_5 UINT64_C(0xffffffffffffffe0)
395 #define NPI_PORT_BP_CONTROL_BP_ON UINT64_C(0x0000000000000010)
396 #define NPI_PORT_BP_CONTROL_ENB UINT64_C(0x000000000000000f)
398 #define NPI_PORT32_INSTR_HDR_XXX_63_44 UINT64_C(0xfffff00000000000)
399 #define NPI_PORT32_INSTR_HDR_PBP UINT64_C(0x0000080000000000)
400 #define NPI_PORT32_INSTR_HDR_XXX_42_38 UINT64_C(0x000007c000000000)
401 #define NPI_PORT32_INSTR_HDR_RPARMODE UINT64_C(0x0000003000000000)
402 #define NPI_PORT32_INSTR_HDR_XXX_35 UINT64_C(0x0000000800000000)
403 #define NPI_PORT32_INSTR_HDR_RSKP_LEN UINT64_C(0x00000007f0000000)
404 #define NPI_PORT32_INSTR_HDR_XXX_27_22 UINT64_C(0x000000000fc00000)
405 #define NPI_PORT32_INSTR_HDR_USE_IHDR UINT64_C(0x0000000000200000)
406 #define NPI_PORT32_INSTR_HDR_XXX_20_16 UINT64_C(0x00000000001f0000)
407 #define NPI_PORT32_INSTR_HDR_PAR_MODE UINT64_C(0x000000000000c000)
408 #define NPI_PORT32_INSTR_HDR_XXX_13 UINT64_C(0x0000000000002000)
409 #define NPI_PORT32_INSTR_HDR_SKP_LEN UINT64_C(0x0000000000001fc0)
410 #define NPI_PORT32_INSTR_HDR_XXX_5_0 UINT64_C(0x000000000000003f)
412 #define NPI_BIST_STATUS_XXX_63_20 UINT64_C(0xfffffffffff00000)
413 #define NPI_BIST_STATUS_CSR_BS UINT64_C(0x0000000000080000)
414 #define NPI_BIST_STATUS_DIF_BS UINT64_C(0x0000000000040000)
415 #define NPI_BIST_STATUS_RDP_BS UINT64_C(0x0000000000020000)
416 #define NPI_BIST_STATUS_PCNC_BS UINT64_C(0x0000000000010000)
417 #define NPI_BIST_STATUS_PCN_BS UINT64_C(0x0000000000008000)
418 #define NPI_BIST_STATUS_RDN_BS UINT64_C(0x0000000000004000)
419 #define NPI_BIST_STATUS_PCAC_BS UINT64_C(0x0000000000002000)
420 #define NPI_BIST_STATUS_PCAD_BS UINT64_C(0x0000000000001000)
421 #define NPI_BIST_STATUS_RDNL_BS UINT64_C(0x0000000000000800)
422 #define NPI_BIST_STATUS_PGF_BS UINT64_C(0x0000000000000400)
423 #define NPI_BIST_STATUS_PIG_BS UINT64_C(0x0000000000000200)
424 #define NPI_BIST_STATUS_POF0_BS UINT64_C(0x0000000000000100)
425 #define NPI_BIST_STATUS_POF1_BS UINT64_C(0x0000000000000080)
426 #define NPI_BIST_STATUS_POF2_BS UINT64_C(0x0000000000000040)
427 #define NPI_BIST_STATUS_POF3_BS UINT64_C(0x0000000000000020)
428 #define NPI_BIST_STATUS_POS_BS UINT64_C(0x0000000000000010)
429 #define NPI_BIST_STATUS_NUS_BS UINT64_C(0x0000000000000008)
430 #define NPI_BIST_STATUS_DOB_BS UINT64_C(0x0000000000000004)
431 #define NPI_BIST_STATUS_PDF_BS UINT64_C(0x0000000000000002)
432 #define NPI_BIST_STATUS_DPI_BS UINT64_C(0x0000000000000001)
Indexes created Sat Nov 08 12:09:53 GMT 2025