Lines Matching refs:MIPS32
156 # if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0
163 #elif (MIPS32 + MIPS64) > 0
288 #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
484 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
604 #define MIPS_COP_0_WATCH_LO1 _(18), 1 /* MIPS32/64 optional */
606 #define MIPS_COP_0_WATCH_HI1 _(19), 1 /* MIPS32/64 optional */
617 /* MIPS32/64 */
834 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0
840 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0
942 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
Indexes created Tue Oct 21 15:09:54 GMT 2025