Lines Matching defs:writereg
119 writereg(uint32_t reg, uint32_t val)
404 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
405 writereg(reg + JZ_GPIO_MASKS, mask);
406 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */
416 writereg(reg, mask);
425 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
426 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
427 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */
428 writereg(reg + JZ_GPIO_PAT0C, mask);
437 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
438 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
439 writereg
440 writereg(reg + JZ_GPIO_PAT0S, mask);
449 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
450 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
451 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */
452 writereg(reg + JZ_GPIO_PAT0C, mask);
461 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
462 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
463 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */
464 writereg(reg + JZ_GPIO_PAT0S, mask);
473 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */
474 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */
475 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */
476 writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */
477 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */
478 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */
487 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */
488 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */
489 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */
490 writereg(reg + JZ_GPIO_PAT0C, mask); /* trigger on low */
491 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */
492 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */
501 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */
502 writereg(reg + JZ_GPIO_INTC, mask); /* not an interrupt */
503 writereg(reg + JZ_GPIO_PAT1S, mask); /* use as input */
504 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it just in case */