Cross Reference: /src/sys/arch/mips/mips/cache

Lines Matching refs:eva
87 	vaddr_t eva = va + mci->mci_picache_way_size;
93 	while (va < eva) {
104 	vaddr_t eva = round_line(va + size);
108 	mips_dcache_wb_range(va, (eva - va));
112 	while (va < eva) {
122 	vaddr_t eva, orig_va;
126 	eva = round_line(va + size);
129 	mips_dcache_wbinv_range_index(va, (eva - va));
141 	eva = round_line(va + size);
144 	while (va < eva) {
163 	vaddr_t eva = va + mci->mci_pdcache_way_size;
165 	while (va < eva) {
176 	vaddr_t eva = round_line(va + size);
180 	while (va < eva) {
190 	vaddr_t eva;
200 	eva = round_line(va + size);
203 	while (va < eva) {
214 	vaddr_t eva = round_line(va + size);
218 	while (va < eva) {
227 	vaddr_t eva = round_line(va + size);
231 	while (va < eva) {
249 	vaddr_t eva = va + mci->mci_sdcache_way_size;
252 	while (va < eva) {
264 	vaddr_t eva = round_line(va + size);
269 	while (va < eva) {
279 	vaddr_t eva;
290 	eva = round_line(va + size);
293 	while (va < eva) {
305 	vaddr_t eva = round_line(va + size);
310 	while (va < eva) {
320 	vaddr_t eva = round_line(va + size);
325 	while (va < eva) {
OpenGrok
