Lines Matching refs:A0
67 * a0 = SR bits to be cleared for this IPL
69 * Can only use a0-a3 and v0-v1
81 xor a0, v1 # disable ipl's masked bits
82 DYNAMIC_STATUS_MASK(a0,v0) # machine dependent masking
96 mtc0 a0, MIPS_COP_0_STATUS # store back
106 and a0, v1 # a1 contains bit that MBZ
107 3: bnez a0, 3b # loop forever
116 sltiu v0, a0, IPL_HIGH+1 # v0 = a0 <= IPL_HIGH
124 beq a0, a2, 2f # if same, nothing to do
127 sltu v0, a0, a2 # v0 = a0 < a2
132 sll a2, a0, INT_SCALESHIFT # convert IPL to array offset
148 INT_S a0, CPU_INFO_CPL(a3) # save IPL in cpu_info (KSEG0)
158 sll a2, a0, INT_SCALESHIFT # convert IPL to array offset
177 mfc0 a0, MIPS_COP_0_STATUS
179 or v0, a0, v1
211 or v0, v0, a0 # set soft intr. bits
230 nor a0, zero, a0 # bitwise inverse of A0
231 and v0, v0, a0 # clear soft intr. bits
240 tgeiu a0, IPL_HIGH+1
242 move a1, a0
244 sll a2, a0, INT_SCALESHIFT
247 INT_L a0, (v1)
260 and a0, v1, MIPS_INT_MASK # select all interrupts
261 xor a0, v1 # clear all interrupts
262 DYNAMIC_STATUS_MASK(a0,a2) # machine dependent masking
263 mtc0 a0, MIPS_COP_0_STATUS # store back
288 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_DDB
295 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_SCHED
302 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_VM
309 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_SOFTSERIAL
316 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_SOFTNET
323 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_SOFTBIO
330 INT_L a0, _C_LABEL(ipl_sr_map) + 4*IPL_SOFTCLOCK
367 INT_S v1, (a0) # return a new pending mask
Indexes created Wed Oct 22 13:09:56 GMT 2025