Cross Reference: /src/sys/arch/mips/sibyte/dev/sbscn.c

Lines Matching defs:READ_REG
247 #define	READ_REG(rp)		(mips3_ld((register_t)(rp)))
255     ((~READ_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x280))) & (ch)->ch_i_mask)
1139 	while (ISSET(READ_REG(ch->ch_base + 0x20), 0x01)
1146 		    READ_REG(ch->ch_base + 0x60);
1266 		while (ch->ch_tbc && READ_REG(ch->ch_base + 0x20) & 0x04) {
1489 	isr = READ_REG(ch->ch_isr_base) & ch->ch_imr;
1502 			sr = READ_REG(ch->ch_base + 0x20);
1509 					(void)READ_REG(ch->ch_base + 0x60);
1516 					(void)READ_REG(ch->ch_base + 0x60);
1526 					put[0] = READ_REG(ch->ch_base + 0x60);
1533 					sr = READ_REG(ch->ch_base + 0x20);
1616 	} while ((isr = (READ_REG(ch->ch_isr_base) & ch->ch_imr)) != 0);
1624 	sr = READ_REG(ch->ch_base + 0x20);
1645 			    READ_REG(ch->ch_base + 0x20) & 0x04) {
1688 	while ((READ_REG(base + 0x20) & 0x01) == 0)
1691 	c = READ_REG(base + 0x60) & 0xff;
1705 	while ((READ_REG(base + 0x20) & 0x08) == 0 && --timo)
1712 	while ((READ_REG(base + 0x20) & 0x08) == 0 && --timo)
1736 	while ((READ_REG(chanregbase + 0x20) & 0x08) == 0 && --timo)
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