Cross Reference: /src/sys/arch/mips/sibyte/dev/sbscn.c

Lines Matching defs:WRITE_REG
248 #define	WRITE_REG(rp, val)	(mips3_sd((register_t)(rp), (val)))
264 	WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2c0),	\
266 	WRITE_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x2b0),	\
296 	WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x270), 0);
298 	WRITE_REG(MIPS_PHYS_TO_KSEG1(sc->sc_addr + 0x210), 0x0f); /* XXX */
337 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
472 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
486 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
542 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
595 		WRITE_REG(ch->ch_imr_base, ch->ch_imr);
836 		WRITE_REG(ch->ch_base + 0x50, 0x60);
838 		WRITE_REG(ch->ch_base + 0x50, 0x70);
1161 	WRITE_REG(ch->ch_imr_base, 0);
1164 	WRITE_REG(ch->ch_base + 0x00, ch->ch_mode1);
1165 	WRITE_REG(ch->ch_base + 0x10, ch->ch_mode2);
1166 	WRITE_REG(ch->ch_base + 0x30, ch->ch_brc);
1171 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1259 		WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1269 			WRITE_REG(ch->ch_base + 0x70, c);
1399 				WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1570 					WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1575 				WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1582 			WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1649 				WRITE_REG(ch->ch_base + 0x70, c);
1653 				WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1708 	WRITE_REG(base + 0x70, c);
1731 	WRITE_REG(imaskreg, 0);			/* disable channel intrs */
1744 	WRITE_REG(chanregbase + 0x50, 2 << 4);	/* reset receiver */
1745 	WRITE_REG(chanregbase + 0x50, 3 << 4);	/* reset transmitter */
1750 	WRITE_REG(chanregbase + 0x00, mode1);
1751 	WRITE_REG(chanregbase + 0x10, mode2);
1752 	WRITE_REG(chanregbase + 0x30, brc);
1757 	WRITE_REG(chanregbase + 0x50,M_DUART_RX_EN | M_DUART_TX_EN);
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