Cross Reference: /src/sys/arch/mips/sibyte/dev/sbscn.c

Lines Matching refs:ch_imr
336 	ch->ch_imr = 0;
337 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
468 	ch->ch_imr = 0x04;
470 	ch->ch_imr = 0x00;
472 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
485 	ch->ch_imr = 0x00;
486 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
535 		ch->ch_imr = 0x04; /* interrupt on break */
537 		ch->ch_imr = 0x00;
541 		ch->ch_imr = 0;
542 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
591 		ch->ch_imr = 0xe;
593 		ch->ch_imr = 0x2;
595 		WRITE_REG(ch->ch_imr_base, ch->ch_imr);
931 	if (ch->ch_imr != 0)
1171 	WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1257 	if (!ISSET(ch->ch_imr, 0x1)) {
1258 		SET(ch->ch_imr, 0x1);
1259 		WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1398 				SET(ch->ch_imr, 0x02);
1399 				WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1489 	isr = READ_REG(ch->ch_isr_base) & ch->ch_imr;
1569 					CLR(ch->ch_imr, 0x02);
1570 					WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1574 				CLR(ch->ch_imr, 0x02);
1575 				WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1581 			CLR(ch->ch_imr, 0x01);
1582 			WRITE_REG(ch->ch_imr_base, ch->ch_imr);
1616 	} while ((isr = (READ_REG(ch->ch_isr_base) & ch->ch_imr)) != 0);
1652 				SET(ch->ch_imr, 0x01);
1653 				WRITE_REG(ch->ch_imr_base, ch->ch_imr);
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