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Lines Matching refs:CSR_WRITE_1

47 #define CSR_WRITE_1(l, r, v)	out8((l)->csr+(r), (v))
230 	CSR_WRITE_1(l, VR_CTL1, val);
276 	CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR);
277 	CSR_WRITE_1(l, VR_CAMADR, CAM_EN | SADR_CAM | 0);
279 		CSR_WRITE_1(l, VR_CAM0 + i, en[i]);
280 	CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR | CAMCTL_WR);
285 	CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_VBIT);
286 	CSR_WRITE_1(l, VR_CAM0, 01);
288 		CSR_WRITE_1(l, VR_CAM0 + i, 00);
289 	CSR_WRITE_1(l, VR_CAMADR, 0);
290 	CSR_WRITE_1(l, VR_CAMCTL, 0);
300 	CSR_WRITE_1(l, VR_RDCSR, 01);
301 	CSR_WRITE_1(l, VR_RDCSR, 04);
303 	CSR_WRITE_1(l, VR_RCR, RCR_AP);
304 	CSR_WRITE_1(l, VR_TCR, 0);
305 	CSR_WRITE_1(l, VR_CTL0 + 0x4, CTL0_STOP);
306 	CSR_WRITE_1(l, VR_CTL0, CTL0_TXON | CTL0_RXON | CTL0_START);
400 	CSR_WRITE_1(l, VR_MIICR, 0);
401 	CSR_WRITE_1(l, VR_MIIADR, 1U << 7);
406 	CSR_WRITE_1(l, VR_MIICR, MIICR_MAUTO);
418 	CSR_WRITE_1(l, VR_MIICR, 0);
431 	CSR_WRITE_1(l, VR_MIICFG, phy);
432 	CSR_WRITE_1(l, VR_MIIADR, reg);
433 	CSR_WRITE_1(l, VR_MIICR, MIICR_RCMD);
449 	CSR_WRITE_1(l, VR_MIICFG, phy);
450 	CSR_WRITE_1(l, VR_MIIADR, reg);
451 	CSR_WRITE_1(l, VR_MIICR, MIICR_WCMD);