1 /* $NetBSD: vge.c,v 1.3 2011/10/30 21:08:33 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 34 #include <netinet/in.h> 35 #include <netinet/in_systm.h> 36 37 #include <lib/libsa/stand.h> 38 #include <lib/libsa/net.h> 39 40 #include "globals.h" 41 42 /* 43 * - reverse endian access every CSR. 44 * - no vtophys() translation, vaddr_t == paddr_t. 45 * - PIPT writeback cache aware. 46 */ 47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v)) 48 #define CSR_READ_1(l, r) in8((l)->csr+(r)) 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 52 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 53 #define VTOPHYS(va) (uint32_t)(va) 54 #define DEVTOV(pa) (uint32_t)(pa) 55 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 56 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 57 #define DELAY(n) delay(n) 58 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 59 60 struct tdesc { 61 uint32_t t0, t1; 62 struct { 63 uint32_t lo; 64 uint32_t hi; 65 } tf[7]; 66 }; 67 struct rdesc { 68 uint32_t r0, r1, r2, r3; 69 }; 70 #define T0_OWN (1U << 31) /* 1: loaded for HW to send */ 71 #define T0_TERR (1U << 15) /* Tx error summary */ 72 #define T0_UDF (1U << 12) /* found link down when Tx */ 73 #define T0_SHDN (1U << 10) /* transfer was shutdowned */ 74 #define T0_CRS (1U << 9) /* found carrier sense lost */ 75 #define T0_CDH (1U << 8) /* heartbeat check failure */ 76 #define T0_ABT (1U << 7) /* excessive collision Tx abort */ 77 #define T0_OWT (1U << 6) /* jumbo Tx frame was aborted */ 78 #define T0_OWC (1U << 5) /* found out of window collision */ 79 #define T0_COLS (1U << 4) /* collision detected */ 80 #define T0_NCRMASK 0xf /* number of collision retries */ 81 #define T1_EOF (1U << 25) /* TCP large last segment */ 82 #define T1_SOF (1U << 24) /* TCP large first segment */ 83 #define T1_TIC (1U << 13) /* post Tx done interrupt */ 84 #define T1_PIC (1U << 22) /* post priority interrupt */ 85 #define T1_VTAG (1U << 21) /* insert VLAG tag */ 86 #define T1_IPCK (1U << 20) /* generate IPv4 csum */ 87 #define T1_UDPCK (1U << 19) /* generate UDPv4 csum */ 88 #define T1_TCPCK (1U << 18) /* generate TCPv4 csum */ 89 #define T1_JUMBO (1U << 17) /* jumbo frame */ 90 #define T1_CRC (1U << 16) /* _disable_ CRC generation */ 91 #define T1_PRIO 0x0000e000 /* VLAN priority value */ 92 #define T1_CFI (1U << 12) /* VLAN CFI */ 93 #define T1_VID 0x00000fff /* VLAN ID 11:0 */ 94 #define T_FLMASK 0x00003fff /* Tx frame/segment length */ 95 #define TF0_Q (1U << 31) /* "Q" bit of tf[0].hi */ 96 97 #define R0_OWN (1U << 31) /* 1: empty for HW to load anew */ 98 #define R0_FLMASK 0x3fff0000 /* frame length */ 99 #define R0_RXOK (1U << 15) 100 #define R0_MAR (1U << 13) /* multicast frame */ 101 #define R0_BAR (1U << 12) /* broadcast frame */ 102 #define R0_PHY (1U << 11) /* unicast frame */ 103 #define R0_VTAG (1U << 10) /* VTAG indicator */ 104 #define R0_STP (1U << 9) /* first frame segment */ 105 #define R0_EDP (1U << 8) /* last frame segment */ 106 #define R0_DETAG (1U << 7) /* VTAG has removed */ 107 #define R0_SNTAG (1U << 6) /* tagged SNAP frame */ 108 #define R0_SYME (1U << 5) /* symbol error */ 109 #define R0_LENE (1U << 4) /* frame length error */ 110 #define R0_CSUME (1U << 3) /* TCP/IP bad csum */ 111 #define R0_FAE (1U << 2) /* frame alignment error */ 112 #define R0_CRCE (1U << 1) /* CRC error */ 113 #define R0_VIDM (1U << 0) /* VTAG filter miss */ 114 #define R1_IPOK (1U << 22) /* IP csum was fine */ 115 #define R1_TUPOK (1U << 21) /* TCP/UDP csum was fine */ 116 #define R1_FRAG (1U << 20) /* fragmented IP */ 117 #define R1_CKSMZO (1U << 19) /* UDP csum field was zero */ 118 #define R1_IPKT (1U << 18) /* frame was IPv4 */ 119 #define R1_TPKT (1U << 17) /* frame was TCPv4 */ 120 #define R1_UPKT (1U << 16) /* frame was UDPv4 */ 121 #define R3_IC (1U << 31) /* post Rx interrupt */ 122 #define R_FLMASK 0x00003ffd /* Rx segment buffer length */ 123 124 #define VR_PAR0 0x00 /* SA [0] */ 125 #define VR_PAR1 0x01 /* SA [1] */ 126 #define VR_PAR2 0x02 /* SA [2] */ 127 #define VR_PAR3 0x03 /* SA [3] */ 128 #define VR_PAR4 0x04 /* SA [4] */ 129 #define VR_PAR5 0x05 /* SA [5] */ 130 #define VR_CAM0 0x10 /* 0..7 */ 131 #define VR_RCR 0x06 /* Rx control */ 132 #define RCR_AP (1U << 6) /* accept unicast frame */ 133 #define RCR_AL (1U << 5) /* accept long VTAG frame */ 134 #define RCR_PROM (1U << 4) /* accept any frame */ 135 #define RCR_AB (1U << 3) /* accept broadcast frame */ 136 #define RCR_AM (1U << 2) /* use multicast filter */ 137 #define VR_TCR 0x07 /* Tx control */ 138 #define VR_CTL0 0x08 /* control #0 */ 139 #define CTL0_TXON (1U << 3) /* enable Tx DMA */ 140 #define CTL0_RXON (1U << 2) /* enable Rx DMA */ 141 #define CTL0_STOP (1U << 1) /* activate stop processing */ 142 #define CTL0_START (1U << 0) /* start and activate */ 143 #define VR_CTL1 0x09 /* control #1 */ 144 #define CTL1_RESET (1U << 7) 145 #define CTL1_DPOLL (1U << 3) /* _disable_ TDES/RDES polling */ 146 #define VR_CTL2 0x0a /* control #2 */ 147 #define CTL2_3XFLC (1U << 7) /* 802.3x PAUSE flow control */ 148 #define CTL2_TPAUSE (1U << 6) /* handle PAUSE on transmit side */ 149 #define CTL2_RPAUSE (1U << 5) /* handle PAUSE on receive side */ 150 #define CTL2_HDXFLC (1U << 4) /* HDX jabber flow control */ 151 #define VR_CTL3 0x0b /* control #3 */ 152 #define CTL3_GIEN (1U << 1) /* global interrupt enable */ 153 #define VR_DESCHI 0x18 /* RDES/TDES base high 63:32 */ 154 #define VR_DATAHI 0x1c /* frame data base high 63:48 */ 155 #define VR_ISR 0x24 /* ISR0123 */ 156 #define VR_IEN 0x28 /* IEN0123 */ 157 #define VR_TDCSR 0x30 158 #define VR_RDCSR 0x32 159 #define VR_RDB 0x38 /* RDES base lo 31:0 */ 160 #define VR_TDB0 0x40 /* #0 TDES base lo 31:0 */ 161 #define VR_RDCSIZE 0x50 /* 0..255 */ 162 #define VR_TDCSIZE 0x52 /* 0..4095 */ 163 #define VR_RBRDU 0x5e /* 0..255 */ 164 #define VR_CAMADR 0x68 165 #define CAM_EN (1U << 7) /* enable to manipulate */ 166 #define SADR_CAM (0U << 6) /* station address table */ 167 #define VTAG_CAM (1U << 6) /* VLAN tag table */ 168 #define VR_CAMCTL 0x69 169 #define CAMCTL_MULT (00U << 6) /* multicast address hash */ 170 #define CAMCTL_VBIT (01U << 6) /* valid bitmask */ 171 #define CAMCTL_ADDR (02U << 6) /* address data */ 172 #define CAMCTL_RD (1U << 3) /* CAM read op, auto cleared */ 173 #define CAMCTL_WR (1U << 2) /* CAM write op, auto cleared */ 174 #define VR_MIICFG 0x6c /* PHY number 4:0 */ 175 #define VR_MIISR 0x6d /* MII status */ 176 #define MIISR_MIDLE (1U << 7) /* not in auto polling */ 177 #define VR_PHYSR0 0x6e /* PHY status 0 */ 178 #define VR_MIICR 0x70 /* MII control */ 179 #define MIICR_MAUTO (1U << 7) /* activate autopoll mode */ 180 #define MIICR_RCMD (1U << 6) /* MII read operation */ 181 #define MIICR_WCMD (1U << 5) /* MII write operation */ 182 #define VR_MIIADR 0x71 /* MII indirect */ 183 #define VR_MIIDATA 0x72 /* MII read/write */ 184 185 #define FRAMESIZE 1536 186 #define NRXDESC 4 /* HW demands multiple of 4 */ 187 188 struct local { 189 struct tdesc txd; 190 struct rdesc rxd[NRXDESC]; 191 uint8_t rxstore[NRXDESC][FRAMESIZE]; 192 unsigned csr, rx; 193 unsigned phy, bmsr, anlpar; 194 }; 195 196 static void mii_autopoll(struct local *); 197 static void mii_stoppoll(struct local *); 198 static int mii_read(struct local *, int, int); 199 static void mii_write(struct local *, int, int, int); 200 static void mii_dealan(struct local *, unsigned); 201 202 int 203 vge_match(unsigned tag, void *data) 204 { 205 unsigned v; 206 207 v = pcicfgread(tag, PCI_ID_REG); 208 switch (v) { 209 case PCI_DEVICE(0x1106, 0x3119): 210 return 1; 211 } 212 return 0; 213 } 214 215 void * 216 vge_init(unsigned tag, void *data) 217 { 218 unsigned val, i, fdx, loop; 219 struct local *l; 220 struct tdesc *txd; 221 struct rdesc *rxd; 222 uint8_t *en; 223 224 225 l = ALLOC(struct local, 64); /* desc alignment */ 226 memset(l, 0, sizeof(struct local)); 227 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */ 228 229 val = CTL1_RESET; 230 CSR_WRITE_1(l, VR_CTL1, val); 231 do { 232 val = CSR_READ_1(l, VR_CTL1); 233 } while (val & CTL1_RESET); 234 235 l->phy = CSR_READ_1(l, VR_MIICFG) & 0x1f; 236 237 en = data; 238 en[0] = CSR_READ_1(l, VR_PAR0); 239 en[1] = CSR_READ_1(l, VR_PAR1); 240 en[2] = CSR_READ_1(l, VR_PAR2); 241 en[3] = CSR_READ_1(l, VR_PAR3); 242 en[4] = CSR_READ_1(l, VR_PAR4); 243 en[5] = CSR_READ_1(l, VR_PAR5); 244 245 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 246 en[0], en[1], en[2], en[3], en[4], en[5]); 247 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, 248 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); 249 250 mii_dealan(l, 5); 251 252 /* speed and duplexity can be seen in MII 28 */ 253 val = mii_read(l, l->phy, 28); 254 fdx = (val >> 5) & 01; 255 switch ((val >> 3) & 03) { 256 case 0: printf("10baseT"); break; 257 case 1: printf("100baseTX"); break; 258 case 2: printf("1000baseT"); break; 259 } 260 if (fdx) 261 printf("-FDX"); 262 printf("\n"); 263 264 txd = &l->txd; 265 rxd = &l->rxd[0]; 266 for (i = 0; i < NRXDESC; i++) { 267 rxd[i].r0 = htole32(R0_OWN); 268 rxd[i].r1 = 0; 269 rxd[i].r2 = htole32(VTOPHYS(l->rxstore[i])); 270 rxd[i].r3 = htole32(FRAMESIZE << 16); 271 } 272 wbinv(l, sizeof(struct local)); 273 l->rx = 0; 274 275 /* set own station address into entry #0 */ 276 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR); 277 CSR_WRITE_1(l, VR_CAMADR, CAM_EN | SADR_CAM | 0); 278 for (i = 0; i < 6; i++) 279 CSR_WRITE_1(l, VR_CAM0 + i, en[i]); 280 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_ADDR | CAMCTL_WR); 281 loop = 20; 282 while (--loop > 0 && (i = CSR_READ_1(l, VR_CAMCTL)) & CAMCTL_WR) 283 DELAY(1); 284 /* mark entry #0 valid, position 0 of 63:0 */ 285 CSR_WRITE_1(l, VR_CAMCTL, CAMCTL_VBIT); 286 CSR_WRITE_1(l, VR_CAM0, 01); 287 for (i = 1; i < 8; i++) 288 CSR_WRITE_1(l, VR_CAM0 + i, 00); 289 CSR_WRITE_1(l, VR_CAMADR, 0); 290 CSR_WRITE_1(l, VR_CAMCTL, 0); 291 292 /* prepare descriptor lists */ 293 CSR_WRITE_4(l, VR_RDB, VTOPHYS(rxd)); 294 CSR_WRITE_2(l, VR_RDCSIZE, NRXDESC - 1); 295 CSR_WRITE_2(l, VR_RBRDU, NRXDESC - 1); 296 CSR_WRITE_4(l, VR_TDB0, VTOPHYS(txd)); 297 CSR_WRITE_2(l, VR_TDCSIZE, 0); 298 299 /* enable transmitter and receiver */ 300 CSR_WRITE_1(l, VR_RDCSR, 01); 301 CSR_WRITE_1(l, VR_RDCSR, 04); 302 CSR_WRITE_2(l, VR_TDCSR, 01); 303 CSR_WRITE_1(l, VR_RCR, RCR_AP); 304 CSR_WRITE_1(l, VR_TCR, 0); 305 CSR_WRITE_1(l, VR_CTL0 + 0x4, CTL0_STOP); 306 CSR_WRITE_1(l, VR_CTL0, CTL0_TXON | CTL0_RXON | CTL0_START); 307 CSR_WRITE_4(l, VR_ISR, ~0); 308 CSR_WRITE_4(l, VR_IEN, 0); 309 310 return l; 311 } 312 313 int 314 vge_send(void *dev, char *buf, unsigned len) 315 { 316 struct local *l = dev; 317 volatile struct tdesc *txd; 318 unsigned loop; 319 320 len = (len & T_FLMASK); 321 if (len < 60) 322 len = 60; /* needs to stretch to ETHER_MIN_LEN - 4 */ 323 wbinv(buf, len); 324 txd = &l->txd; 325 txd->tf[0].lo = htole32(VTOPHYS(buf)); 326 txd->tf[0].hi = htole32(len << 16); 327 txd->t1 = htole32(T1_SOF | T1_EOF | (2 << 28)); 328 txd->t0 = htole32(T0_OWN | len << 16); 329 wbinv(txd, sizeof(struct tdesc)); 330 CSR_WRITE_2(l, VR_TDCSR, 04); 331 loop = 100; 332 do { 333 if ((le32toh(txd->t0) & T0_OWN) == 0) 334 goto done; 335 DELAY(10); 336 inv(txd, sizeof(struct tdesc)); 337 } while (--loop > 0); 338 printf("xmit failed\n"); 339 return -1; 340 done: 341 return len; 342 } 343 344 int 345 vge_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 346 { 347 struct local *l = dev; 348 volatile struct rdesc *rxd; 349 unsigned bound, rxstat, len; 350 uint8_t *ptr; 351 352 bound = 1000 * timo; 353 printf("recving with %u sec. timeout\n", timo); 354 again: 355 rxd = &l->rxd[l->rx]; 356 do { 357 inv(rxd, sizeof(struct rdesc)); 358 rxstat = le32toh(rxd->r0); 359 if ((rxstat & R0_OWN) == 0) 360 goto gotone; 361 DELAY(1000); /* 1 milli second */ 362 } while (--bound > 0); 363 errno = 0; 364 return -1; 365 gotone: 366 if ((rxstat & R0_RXOK) == 0) { 367 rxd->r0 = htole32(R0_OWN); 368 rxd->r1 = 0; 369 wbinv(rxd, sizeof(struct rdesc)); 370 l->rx ^= 1; 371 goto again; 372 } 373 len = ((rxstat & R0_FLMASK) >> 16) - 4 /* HASFCS */; 374 if (len > maxlen) 375 len = maxlen; 376 ptr = l->rxstore[l->rx]; 377 inv(ptr, len); 378 memcpy(buf, ptr, len); 379 if ((l->rx & 03) == 3) { 380 /* needs to set R0_OWN to 4 descriptors at a time */ 381 rxd[00].r0 = htole32(R0_OWN); 382 rxd[00].r1 = 0; 383 rxd[-1].r0 = htole32(R0_OWN); 384 rxd[-1].r1 = 0; 385 rxd[-2].r0 = htole32(R0_OWN); 386 rxd[-2].r1 = 0; 387 rxd[-3].r0 = htole32(R0_OWN); 388 rxd[-3].r1 = 0; 389 wbinv(rxd, NRXDESC * sizeof(struct rdesc)); 390 } 391 l->rx = (l->rx + 1) & (NRXDESC - 1); 392 return len; 393 } 394 395 static void 396 mii_autopoll(struct local *l) 397 { 398 int v; 399 400 CSR_WRITE_1(l, VR_MIICR, 0); 401 CSR_WRITE_1(l, VR_MIIADR, 1U << 7); 402 do { 403 DELAY(1); 404 v = CSR_READ_1(l, VR_MIISR); 405 } while ((v & MIISR_MIDLE) == 0); 406 CSR_WRITE_1(l, VR_MIICR, MIICR_MAUTO); 407 do { 408 DELAY(1); 409 v = CSR_READ_1(l, VR_MIISR); 410 } while ((v & MIISR_MIDLE) != 0); 411 } 412 413 static void 414 mii_stoppoll(struct local *l) 415 { 416 int v; 417 418 CSR_WRITE_1(l, VR_MIICR, 0); 419 do { 420 DELAY(1); 421 v = CSR_READ_1(l, VR_MIISR); 422 } while ((v & MIISR_MIDLE) == 0); 423 } 424 425 static int 426 mii_read(struct local *l, int phy, int reg) 427 { 428 int v; 429 430 mii_stoppoll(l); 431 CSR_WRITE_1(l, VR_MIICFG, phy); 432 CSR_WRITE_1(l, VR_MIIADR, reg); 433 CSR_WRITE_1(l, VR_MIICR, MIICR_RCMD); 434 do { 435 v = CSR_READ_1(l, VR_MIICR); 436 } while (v & MIICR_RCMD); 437 v = CSR_READ_2(l, VR_MIIDATA); 438 mii_autopoll(l); 439 return v; 440 } 441 442 static void 443 mii_write(struct local *l, int phy, int reg, int data) 444 { 445 int v; 446 447 mii_stoppoll(l); 448 CSR_WRITE_2(l, VR_MIIDATA, data); 449 CSR_WRITE_1(l, VR_MIICFG, phy); 450 CSR_WRITE_1(l, VR_MIIADR, reg); 451 CSR_WRITE_1(l, VR_MIICR, MIICR_WCMD); 452 do { 453 v = CSR_READ_1(l, VR_MIICR); 454 } while (v & MIICR_WCMD); 455 mii_autopoll(l); 456 } 457 458 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 459 #define BMCR_RESET 0x8000 /* reset */ 460 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 461 #define BMCR_ISO 0x0400 /* isolate */ 462 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 463 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 464 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 465 #define BMSR_LINK 0x0004 /* Link status */ 466 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 467 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 468 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 469 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 470 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 471 #define ANAR_10 0x0020 /* local device supports 10bT */ 472 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 473 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 474 #define MII_GTCR 0x09 /* 1000baseT control */ 475 #define GANA_1000TFDX 0x0200 /* advertise 1000baseT FDX */ 476 #define GANA_1000THDX 0x0100 /* advertise 1000baseT HDX */ 477 #define MII_GTSR 0x0a /* 1000baseT status */ 478 #define GLPA_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ 479 #define GLPA_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ 480 #define GLPA_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ 481 482 void 483 mii_dealan(struct local *l, unsigned timo) 484 { 485 unsigned anar, gtcr, bound; 486 487 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 488 anar |= ANAR_FC; 489 gtcr = GANA_1000TFDX | GANA_1000THDX; 490 mii_write(l, l->phy, MII_ANAR, anar); 491 mii_write(l, l->phy, MII_GTCR, gtcr); 492 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 493 l->anlpar = 0; 494 bound = getsecs() + timo; 495 do { 496 l->bmsr = mii_read(l, l->phy, MII_BMSR) | 497 mii_read(l, l->phy, MII_BMSR); /* read twice */ 498 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 499 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 500 break; 501 } 502 DELAY(10 * 1000); 503 } while (getsecs() < bound); 504 return; 505 } 506
Indexes created Fri Sep 26 08:10:20 GMT 2025