Cross Reference: /src/sys/arch/sun3/sun3x/pmap.c

Lines Matching defs:b_tbl
1140 	b_tmgr_t *b_tbl;
1144 		b_tbl = &Btmgrbase[i];
1146 		b_tbl->bt_parent = NULL;	/* clear its parent,  */
1147 		b_tbl->bt_pidx = 0;		/* parent index,      */
1148 		b_tbl->bt_wcnt = 0;		/* wired entry count, */
1149 		b_tbl->bt_ecnt = 0;		/* valid entry count. */
1152 		b_tbl->bt_dtbl = &mmuBbase[i * MMU_B_TBL_SIZE];
1156 			b_tbl->bt_dtbl[j].attr.raw = MMU_DT_INVALID;
1159 		TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
1364 	b_tmgr_t	*b_tbl;
1416 				b_tbl = mmuB2tmgr(dtbl);
1417 				bt_wired = b_tbl->bt_wcnt;
1418 				removed_cnt += free_b_table(b_tbl, true);
1444 free_b_table(b_tmgr_t *b_tbl, bool relink)
1453 	bt_wired = b_tbl->bt_wcnt;
1454 	if (b_tbl->bt_ecnt) {
1455 		dte = b_tbl->bt_dtbl;
1463 					b_tbl->bt_wcnt--;
1467 		b_tbl->bt_ecnt = 0;
1469 	KASSERT(b_tbl->bt_wcnt == 0);
1472 		b_tbl->bt_parent = NULL;
1474 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
1475 		TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link);
1606 pmap_stroll(pmap_t pmap, vaddr_t va, a_tmgr_t **a_tbl, b_tmgr_t **b_tbl,
1628 	*b_tbl = mmuB2tmgr(mmu_ptov(a_dte->addr.raw));
1634 	b_dte = &((*b_tbl)->bt_dtbl[*b_idx]);
1663 	b_tmgr_t *b_tbl;         /* B: short descriptor table manager */
1788 		 *                 \- b_tbl -> +-+-  *
1793 		b_tbl = mmuB2tmgr(b_dte);
1801 		if (wired && !b_tbl->bt_wcnt) {
1802 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
1807 		b_tbl = get_b_table();
1810 		a_dte->addr.raw = mmu_vtop(b_tbl->bt_dtbl);
1815 		b_tbl->bt_parent = a_tbl;
1816 		b_tbl->bt_pidx = a_idx;
1835 	b_dte = &b_tbl->bt_dtbl[b_idx]; /* Retrieve descriptor from table */
1841 		 * \- b_tbl -> +-+-+-+-+-+-+-+-+-+-+- *
1855 			b_tbl->bt_wcnt++;
1864 		b_tbl->bt_ecnt++; /* Update parent's valid entry count */
1867 		c_tbl->ct_parent = b_tbl;
1882 			b_tbl->bt_wcnt++;
1922 					if (--b_tbl->bt_wcnt == 0) {
2043 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
2267 	b_tmgr_t *b_tbl;
2316 	b_tbl = NULL;
2321 		if (b_tbl || MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
2322 		  if (b_tbl == NULL) {
2323 		    b_tbl = (b_tmgr_t *) a_tbl->at_dtbl[a_idx].addr.raw;
2324 		    b_tbl = mmu_ptov((vaddr_t)b_tbl);
2325 		    b_tbl = mmuB2tmgr((mmu_short_dte_t *)b_tbl);
2327 		  if (c_tbl || MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) {
2329 		      c_tbl = (c_tmgr_t *) MMU_DTE_PA(b_tbl->bt_dtbl[b_idx]);
2352 		        b_tbl = NULL;
2361 		      b_tbl = NULL;
2366 		  b_tbl = NULL;
2386 	b_tmgr_t *b_tbl;
2399 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl, &pte, &a_idx,
2423 		if (--b_tbl->bt_wcnt == 0) {
2424 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
2942 	b_tmgr_t	*b_tbl;
2949 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl,
3055 	b_tmgr_t *b_tbl;
3112 			b_tbl = mmuB2tmgr(b_dte);
3113 			bt_wired = b_tbl->bt_wcnt;
3124 				empty = pmap_remove_b(b_tbl, sva, eva);
3126 				empty = pmap_remove_b(b_tbl, sva, nstart);
3132 			if (bt_wired && b_tbl->bt_wcnt == 0)
3172 				b_tbl = mmuB2tmgr(b_dte);
3173 				bt_wired = b_tbl->bt_wcnt;
3175 				free_b_table(b_tbl, true);
3218 			b_tbl = mmuB2tmgr(b_dte);
3219 			bt_wired = b_tbl->bt_wcnt;
3221 			empty = pmap_remove_b(b_tbl, nend, eva);
3227 			if (bt_wired && b_tbl->bt_wcnt == 0)
3274 pmap_remove_b(b_tmgr_t *b_tbl, vaddr_t sva, vaddr_t eva)
3287 	bt_wired = b_tbl->bt_wcnt;
3291 		b_dte = &b_tbl->bt_dtbl[idx];
3307 				b_tbl->bt_wcnt--;
3311 				b_tbl->bt_ecnt--;
3317 		b_dte = &b_tbl->bt_dtbl[idx];
3333 					b_tbl->bt_wcnt--;
3336 				b_tbl->bt_ecnt--;
3344 		b_dte = &b_tbl->bt_dtbl[idx];
3356 				b_tbl->bt_wcnt--;
3360 				b_tbl->bt_ecnt--;
3365 	if (b_tbl->bt_ecnt == 0) {
3366 		KASSERT(b_tbl->bt_wcnt == 0);
3367 		b_tbl->bt_parent = NULL;
3369 			TAILQ_REMOVE(&b_pool, b_tbl, bt_link);
3370 		TAILQ_INSERT_HEAD(&b_pool, b_tbl, bt_link);
3378 		if (bt_wired && b_tbl->bt_wcnt == 0)
3379 			TAILQ_INSERT_TAIL(&b_pool, b_tbl, bt_link);
3646 	b_tmgr_t *b_tbl;
3661 	        b_tbl = mmuB2tmgr(mmu_ptov(a_tbl->at_dtbl[a_idx].addr.raw));
3663 	            if (MMU_VALID_DT(b_tbl->bt_dtbl[b_idx])) {
3665 	                    mmu_ptov(MMU_DTE_PA(b_tbl->bt_dtbl[b_idx])));
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