Cross Reference: /src/sys/dev/acpi/qcomgpio.c

Lines Matching defs:qih
525 	struct qcomgpio_intr_handler *qih, *qihp;
538 	qih = kmem_alloc(sizeof(*qih), KM_SLEEP);
539 	qih->ih_func = func;
540 	qih->ih_arg = arg;
541 	qih->ih_pin = pin;
542 	qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ?
544 	snprintf(qih->ih_name, sizeof(qih->ih_name), "pin %d", pin);
549 		if (qihp->ih_pin == qih->ih_pin) {
551 			kmem_free(qih, sizeof(*qih));
558 	LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list);
593 	evcnt_attach_dynamic(&qih->ih_evcnt, EVCNT_TYPE_INTR,
594 	    NULL, device_xname(sc->sc_dev), qih->ih_name);
596 	return qih;
603 	struct qcomgpio_intr_handler *qih = ih;
606 	evcnt_detach(&qih->ih_evcnt);
610 	LIST_REMOVE(qih, ih_list);
612 	val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
614 	WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
618 	kmem_free(qih, sizeof(*qih));
636 	struct qcomgpio_intr_handler *qih = ih;
639 	val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
640 	if (qih->ih_type == IST_LEVEL) {
644 	WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
651 	struct qcomgpio_intr_handler *qih = ih;
654 	val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
655 	if (qih->ih_type == IST_LEVEL) {
659 	WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
666 	struct qcomgpio_intr_handler *qih;
671 	LIST_FOREACH(qih, &sc->sc_intrs, ih_list) {
672 		const int pin = qih->ih_pin;
677 			qih->ih_evcnt.ev_count++;
679 			rv |= qih->ih_func(qih->ih_arg);
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