Cross Reference: /src/sys/dev/ic/anx

Lines Matching refs:sc_dpaux
351 	pedid = drm_get_edid(connector, &sc->sc_dpaux.ddc);
443 	ret = drm_dp_dpcd_write(&sc->sc_dpaux, DP_LINK_BW_SET, bw, sizeof(bw));
465 	drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
479 	drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
490 	    drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
510 	drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
524 	drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
535 	    drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
555 	drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
569 	ret = drm_dp_dpcd_read(&sc->sc_dpaux, DP_DPCD_REV, values,
583 		if (drm_dp_dpcd_readb(&sc->sc_dpaux, DP_SET_POWER, &power) < 0)
587 		if (drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_SET_POWER, power) < 0)
592 	if (DP_RECEIVER_CAP_SIZE != drm_dp_dpcd_read(&sc->sc_dpaux, DP_DPCD_REV,
601 	drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
907 	    sc_dpaux);
1040 	sc->sc_dpaux.name = "DP Aux";
1041 	sc->sc_dpaux.transfer = anxdp_dp_aux_transfer;
1042 	sc->sc_dpaux.dev = sc->sc_dev;
1043 	if (drm_dp_aux_register(&sc->sc_dpaux) != 0) {
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