Lines Matching refs:AR_WRITE
188 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
218 AR_WRITE(sc, AR_PHY(0x37), phy);
235 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
244 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
252 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
263 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
271 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
276 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
280 AR_WRITE(sc, AR_PHY_SETTLING, reg);
285 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
291 AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
295 AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
299 AR_WRITE(sc, AR_PHY_CCA(0), reg);
303 AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg);
310 AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
317 AR_WRITE(sc, AR_PHY_SETTLING, reg);
457 AR_WRITE(sc, AR_PHY_TPCRG1, reg);
475 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
479 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
483 AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg);
503 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
507 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
672 AR_WRITE(sc, AR_PHY_POWER_TX_SUB,
704 AR_WRITE(sc, AR_PHY_SPUR_REG,
717 AR_WRITE(sc, AR_PHY_TIMING11,
743 AR_WRITE(sc, AR_PHY(0), 0x00000007);
745 AR_WRITE(sc, AR_PHY(0x36), 0x00007058);
747 AR_WRITE(sc, AR_PHY(0x20), 0x00010000);
814 AR_WRITE(sc, 0x98b0, 0x1e5795e5);
815 AR_WRITE(sc, 0x98e0, 0x02008020);
818 AR_WRITE(sc, 0x98b0, 0x02108421);
819 AR_WRITE(sc, 0x98ec, 0x00000008);
822 AR_WRITE(sc, 0x98b0, 0x0e73ff17);
823 AR_WRITE(sc, 0x98e0, 0x00000420);
827 AR_WRITE(sc, 0x98f0, 0x01400018);
829 AR_WRITE(sc, 0x98f0, 0x01c00018);
846 AR_WRITE(sc, 0x989c, bank6tpc[i]);
848 AR_WRITE(sc, 0x98d0, 0x0000000f);
850 AR_WRITE(sc, 0x98d0, 0x0010000f);
853 AR_WRITE(sc, 0x989c, 0x00000500);
854 AR_WRITE(sc, 0x989c, 0x00000800);
855 AR_WRITE(sc, 0x98cc, 0x0000000e);
869 AR_WRITE(sc, AR_PHY_BB_RFGAIN(i), pvals[i]);
901 AR_WRITE(sc, 0x989c, rwbank6[i]);
902 AR_WRITE(sc, 0x98d0, 0x0010000f);
961 AR_WRITE(sc, 0x989c, pvals[i]);
962 AR_WRITE(sc, 0x98cc, 0); /* Finalize. */
Indexes created Tue Oct 21 19:09:51 GMT 2025