Cross Reference: /src/sys/dev/ic/arn9285.c

Lines Matching defs:modal
186 	const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
191 	AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
192 	AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain);
195 	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
196 	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
202 		    modal->bswMargin);
204 		    modal->bswAtten);
206 		    modal->xatten2Margin);
208 		    modal->xatten2Db);
214 		    modal->bswMargin);
216 		    modal->bswAtten);
218 		    modal->xatten2Margin);
220 		    modal->xatten2Db);
224 		txRxAtten = modal->txRxAtten;
229 	reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
235 	reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
238 	if (modal->version >= 3) {
243 		    (modal->ob_234  >> 12) & 0x1);
245 		    (modal->db1_234 >> 12) & 0x3);
247 		    (modal->db1_234 >> 14) & 0x3);
249 		    (modal->ob_234  >> 13) & 0x1);
251 		    (modal->ob_234  >> 14) & 0x1);
256 		if (modal->ob_234 & (1 << 15))
263 	if (modal->version >= 2) {
264 		ob [0] = (modal->ob_01   >> 0) & 0xf;
265 		ob [1] = (modal->ob_01   >> 4) & 0xf;
266 		ob [2] = (modal->ob_234  >> 0) & 0xf;
267 		ob [3] = (modal->ob_234  >> 4) & 0xf;
268 		ob [4] = (modal->ob_234  >> 8) & 0xf;
270 		db1[0] = (modal->db1_01  >> 0) & 0xf;
271 		db1[1] = (modal->db1_01  >> 4) & 0xf;
272 		db1[2] = (modal->db1_234 >> 0) & 0xf;
273 		db1[3] = (modal->db1_234 >> 4) & 0xf;
274 		db1[4] = (modal->db1_234 >> 8) & 0xf;
276 		db2[0] = (modal->db2_01  >> 0) & 0xf;
277 		db2[1] = (modal->db2_01  >> 4) & 0xf;
278 		db2[2] = (modal->db2_234 >> 0) & 0xf;
279 		db2[3] = (modal->db2_234 >> 4) & 0xf;
280 		db2[4] = (modal->db2_234 >> 8) & 0xf;
283 	else if (modal->version == 1) {
284 		ob [0] = (modal->ob_01   >> 0) & 0xf;
285 		ob [1] = (modal->ob_01   >> 4) & 0xf;
289 		db1[0] = (modal->db1_01  >> 0) & 0xf;
290 		db1[1] = (modal->db1_01  >> 4) & 0xf;
294 		db2[0] = (modal->db2_01  >> 0) & 0xf;
295 		db2[1] = (modal->db2_01  >> 4) & 0xf;
301 		ob [0] = modal->ob_01;
304 		db1[0] = modal->db1_01;
308 		db2[0] = modal->db1_01;
356 	reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
360 	reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
363 	reg =  SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
364 	reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
365 	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
366 	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
370 	reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
374 	reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
378 	reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
384 		    modal->txFrameToPaOn);
386 		    modal->txFrameToDataStart);
392 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
797 	const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
812 	uint16_t max_ant_gain = modal->antennaGain;
871 			ht40inc = modal->ht40PowerIncForPdadc;
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