Cross Reference: /src/sys/dev/ic/dwiic.c

Lines Matching defs:dwiic_read
150 static uint32_t	dwiic_read(struct dwiic_softc *, int);
167 		sc->ss_hcnt = dwiic_read(sc, DW_IC_SS_SCL_HCNT);
169 		sc->ss_lcnt = dwiic_read(sc, DW_IC_SS_SCL_LCNT);
171 		sc->fs_hcnt = dwiic_read(sc, DW_IC_FS_SCL_HCNT);
173 		sc->fs_lcnt = dwiic_read(sc, DW_IC_FS_SCL_LCNT);
175 		sc->sda_hold_time = dwiic_read(sc, DW_IC_SDA_HOLD);
185 	dwiic_read(sc, DW_IC_CLR_INTR);
228 	dwiic_read(sc, DW_IC_CLR_INTR);
252 dwiic_read(struct dwiic_softc *sc, int offset)
276 	reg = dwiic_read(sc, DW_IC_COMP_TYPE);
295 	reg = dwiic_read(sc, DW_IC_COMP_VERSION);
320 		if ((dwiic_read(sc, DW_IC_ENABLE_STATUS) & 1) == enable)
356 		st = dwiic_read(sc, DW_IC_STATUS);
370 	ic_con = dwiic_read(sc, DW_IC_CON);
377 	dwiic_read(sc, DW_IC_CLR_INTR);
387 		dwiic_read(sc, DW_IC_CLR_INTR);
395 		dwiic_read(sc, DW_IC_CLR_INTR);
409 		tx_limit = sc->tx_fifo_depth - dwiic_read(sc, DW_IC_TXFLR);
432 	tx_limit = sc->tx_fifo_depth - dwiic_read(sc, DW_IC_TXFLR);
471 					rx_avail = dwiic_read(sc, DW_IC_RXFLR);
478 				dwiic_read(sc, DW_IC_CLR_INTR);
489 				dwiic_read(sc, DW_IC_CLR_INTR);
491 				rx_avail = dwiic_read(sc, DW_IC_RXFLR);
507 				resp = dwiic_read(sc, DW_IC_DATA_CMD);
521 			    dwiic_read(sc, DW_IC_TXFLR);
529 				st = dwiic_read(sc, DW_IC_STATUS);
539 			dwiic_read(sc, DW_IC_CLR_INTR);
547 			dwiic_read(sc, DW_IC_CLR_INTR);
560        stat = dwiic_read(sc, DW_IC_INTR_STAT);
563 	       dwiic_read(sc, DW_IC_CLR_RX_UNDER);
565 	       dwiic_read(sc, DW_IC_CLR_RX_OVER);
567 	       dwiic_read(sc, DW_IC_CLR_TX_OVER);
569 	       dwiic_read(sc, DW_IC_CLR_RD_REQ);
571 	       dwiic_read(sc, DW_IC_CLR_TX_ABRT);
573 	       dwiic_read(sc, DW_IC_CLR_RX_DONE);
575 	       dwiic_read(sc, DW_IC_CLR_ACTIVITY);
577 	       dwiic_read(sc, DW_IC_CLR_STOP_DET);
579 	       dwiic_read(sc, DW_IC_CLR_START_DET);
581 	       dwiic_read(sc, DW_IC_CLR_GEN_CALL);
603 	en = dwiic_read(sc, DW_IC_ENABLE);
OpenGrok
