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Lines Matching refs:DFCNTRL

723 	mvi	DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
728 	mvi	DFCNTRL, SCSIEN;
731 	test	DFCNTRL, SCSIEN jnz .;
1312 		test	DFCNTRL, HDMAENACK jz return;
1344 		or	DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1346 		or	DFCNTRL, PRELOADEN|HDMAEN;
1364 	mvi	DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1446 	test	DFCNTRL, SCSIEN jnz data_group_dma_loop;
1463 	test	DFCNTRL, DIRECTION jnz data_phase_finish;
1466 		or	DFCNTRL, FIFOFLUSH;
1510 		test	DFCNTRL, DIRECTION jz target_ITloop;
1619 		 * (DIRECTION set in DFCNTRL). The delay is performed by
1642 		test	DFCNTRL, DIRECTION jz interrupt_return;
1643 		and	DFCNTRL, ~SCSIEN;
1648 		or	DFCNTRL, SCSIEN;
1707 	mvi	DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1729 	mvi	DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1788 		or	DFCNTRL, FIFOFLUSH;
1796 	test	DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1886 		or	DFCNTRL, FIFOFLUSH;
1995 		mvi	DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
2001 		or	DFCNTRL, PRELOADEN;