Cross Reference: /src/sys/dev/pci/cxgb/cxgb

Lines Matching defs:txqs
874 txq_prod(struct sge_txq *txq, unsigned int ndesc, struct txq_state *txqs)
881     txqs->gen = txq->gen;
883     txqs->compl = (txq->unacked & 8) << (S_WR_COMPL - 3);
885     txqs->pidx = txq->pidx;
1067  *  @txqs: txq state (generation and producer index)
1082 write_wr_hdr_sgl(unsigned int ndesc, struct tx_desc *txd, struct txq_state *txqs,
1088     struct tx_sw_desc *txsd = &txq->sdesc[txqs->pidx];
1095             V_WR_GEN(txqs->gen)) | wr_lo;
1097         wr_gen2(txd, txqs->gen);
1099         unsigned int ogen = txqs->gen;
1120             if (++txqs->pidx == txq->size) {
1121                 txqs->pidx = 0;
1122                 txqs->gen ^= 1;
1138                 V_WR_GEN(txqs->gen)) | wr_lo;
1139             wr_gen2(txd, txqs->gen);
1161     struct txq_state txqs;
1250             txq_prod(txq, 1, &txqs);
1251             txq->sdesc[txqs.pidx].m = NULL;
1262                       F_WR_SOP | F_WR_EOP | txqs.compl);
1265                 V_WR_GEN(txqs.gen) | V_WR_TID(txq->token));
1267             wr_gen2(txd, txqs.gen);
1288     txq_prod(txq, ndesc, &txqs);
1289     txsd = &txq->sdesc[txqs.pidx];
1290     wr_hi = htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | txqs.compl);
1293     m_set_priority(m0, txqs.pidx);
1295     write_wr_hdr_sgl(ndesc, txd, &txqs, txq, sgl, flits, sgl_flits, wr_hi, wr_lo);
1724     struct txq_state txqs;
1743     txqs.gen = q->gen;
1744     txqs.pidx = q->pidx;
1745     txqs.compl = (q->unacked & 8) << (S_WR_COMPL - 3);
1746     write_wr_hdr_sgl(ndesc, d, &txqs, q, sgl, flits, sgl_flits,
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